16c0a032aSEnric Balletbò i Serra /* 26c0a032aSEnric Balletbò i Serra * (C) Copyright 2010 36c0a032aSEnric Balletbò i Serra * Texas Instruments Incorporated. 46c0a032aSEnric Balletbò i Serra * Aneesh V <aneesh@ti.com> 56c0a032aSEnric Balletbò i Serra * Steve Sakoman <steve@sakoman.com> 66c0a032aSEnric Balletbò i Serra * 76c0a032aSEnric Balletbò i Serra * TI OMAP4 common configuration settings 86c0a032aSEnric Balletbò i Serra * 96c0a032aSEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 106c0a032aSEnric Balletbò i Serra */ 116c0a032aSEnric Balletbò i Serra 126c0a032aSEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP4_COMMON_H 136c0a032aSEnric Balletbò i Serra #define __CONFIG_TI_OMAP4_COMMON_H 146c0a032aSEnric Balletbò i Serra 156c0a032aSEnric Balletbò i Serra /* 166c0a032aSEnric Balletbò i Serra * High Level Configuration Options 176c0a032aSEnric Balletbò i Serra */ 186c0a032aSEnric Balletbò i Serra #define CONFIG_OMAP4430 1 /* which is in a 4430 */ 196c0a032aSEnric Balletbò i Serra #define CONFIG_MISC_INIT_R 206c0a032aSEnric Balletbò i Serra 216c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SYS_L2CACHE_OFF 226c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_L2_PL310 1 236c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_PL310_BASE 0x48242000 246c0a032aSEnric Balletbò i Serra #endif 256c0a032aSEnric Balletbò i Serra 266c0a032aSEnric Balletbò i Serra /* Get CPU defs */ 276c0a032aSEnric Balletbò i Serra #include <asm/arch/cpu.h> 286c0a032aSEnric Balletbò i Serra #include <asm/arch/omap.h> 296c0a032aSEnric Balletbò i Serra 306c0a032aSEnric Balletbò i Serra /* Use General purpose timer 1 */ 316c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE GPT2_BASE 326c0a032aSEnric Balletbò i Serra 336c0a032aSEnric Balletbò i Serra /* 346c0a032aSEnric Balletbò i Serra * Total Size Environment - 128k 356c0a032aSEnric Balletbò i Serra */ 366c0a032aSEnric Balletbò i Serra #define CONFIG_ENV_SIZE (128 << 10) 376c0a032aSEnric Balletbò i Serra 386c0a032aSEnric Balletbò i Serra /* 396c0a032aSEnric Balletbò i Serra * For the DDR timing information we can either dynamically determine 406c0a032aSEnric Balletbò i Serra * the timings to use or use pre-determined timings (based on using the 416c0a032aSEnric Balletbò i Serra * dynamic method. Default to the static timing infomation. 426c0a032aSEnric Balletbò i Serra */ 436c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 446c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 456c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION 466c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 476c0a032aSEnric Balletbò i Serra #endif 486c0a032aSEnric Balletbò i Serra 499a0f4004SNishanth Menon #include <configs/ti_armv7_omap.h> 506c0a032aSEnric Balletbò i Serra 516c0a032aSEnric Balletbò i Serra /* 526c0a032aSEnric Balletbò i Serra * Hardware drivers 536c0a032aSEnric Balletbò i Serra */ 54c7b9686dSThomas Chou #define CONFIG_SYS_NS16550_CLK 48000000 5553ee6342STom Rini #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) 566c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_SERIAL 576c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE (-4) 586c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM3 UART3_BASE 5953ee6342STom Rini #endif 6053ee6342STom Rini #define CONFIG_CONS_INDEX 3 616c0a032aSEnric Balletbò i Serra 626c0a032aSEnric Balletbò i Serra /* TWL6030 */ 636c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SPL_BUILD 646c0a032aSEnric Balletbò i Serra #define CONFIG_TWL6030_POWER 1 656c0a032aSEnric Balletbò i Serra #endif 666c0a032aSEnric Balletbò i Serra 676c0a032aSEnric Balletbò i Serra /* USB */ 6895de1e2fSPaul Kocialkowski #define CONFIG_USB_MUSB_UDC 1 696c0a032aSEnric Balletbò i Serra #define CONFIG_USB_OMAP3 1 706c0a032aSEnric Balletbò i Serra 716c0a032aSEnric Balletbò i Serra /* USB device configuration */ 726c0a032aSEnric Balletbò i Serra #define CONFIG_USB_DEVICE 1 736c0a032aSEnric Balletbò i Serra #define CONFIG_USB_TTY 1 746c0a032aSEnric Balletbò i Serra 756c0a032aSEnric Balletbò i Serra /* 766c0a032aSEnric Balletbò i Serra * Environment setup 776c0a032aSEnric Balletbò i Serra */ 782a1a29c5STom Rini #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ 792a1a29c5STom Rini "bootcmd_" #devtypel #instance "=" \ 802a1a29c5STom Rini "setenv mmcdev " #instance"; "\ 812a1a29c5STom Rini "setenv bootpart " #instance":2 ; "\ 822a1a29c5STom Rini "run mmcboot\0" 832a1a29c5STom Rini 842a1a29c5STom Rini #define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ 852a1a29c5STom Rini #devtypel #instance " " 862a1a29c5STom Rini 872a1a29c5STom Rini #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ 882a1a29c5STom Rini #devtypel #instance " " 892a1a29c5STom Rini 902a1a29c5STom Rini #define BOOT_TARGET_DEVICES(func) \ 912a1a29c5STom Rini func(MMC, mmc, 0) \ 922a1a29c5STom Rini func(LEGACY_MMC, legacy_mmc, 0) \ 932a1a29c5STom Rini func(MMC, mmc, 1) \ 942a1a29c5STom Rini func(LEGACY_MMC, legacy_mmc, 1) \ 952a1a29c5STom Rini func(PXE, pxe, na) \ 962a1a29c5STom Rini func(DHCP, dhcp, na) 972a1a29c5STom Rini 982a1a29c5STom Rini #define CONFIG_BOOTCOMMAND \ 991e93cc84SLokesh Vutla "if test ${boot_fit} -eq 1; then " \ 1001e93cc84SLokesh Vutla "run update_to_fit;" \ 1011e93cc84SLokesh Vutla "fi;" \ 1022a1a29c5STom Rini "run findfdt; " \ 10318c534bbSLokesh Vutla "run envboot; " \ 1042a1a29c5STom Rini "run distro_bootcmd" 1052a1a29c5STom Rini 1062a1a29c5STom Rini #include <config_distro_bootcmd.h> 107*88fdfcd2SSekhar Nori #include <environment/ti/mmc.h> 1082a1a29c5STom Rini 1096c0a032aSEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \ 110fb3ad9bdSTom Rini DEFAULT_LINUX_BOOT_ENV \ 11185d17be3SLokesh Vutla DEFAULT_MMC_TI_ARGS \ 1121e93cc84SLokesh Vutla DEFAULT_FIT_TI_ARGS \ 1136c0a032aSEnric Balletbò i Serra "console=ttyO2,115200n8\0" \ 1146c0a032aSEnric Balletbò i Serra "fdtfile=undefined\0" \ 1156c0a032aSEnric Balletbò i Serra "bootpart=0:2\0" \ 1166c0a032aSEnric Balletbò i Serra "bootdir=/boot\0" \ 1176c0a032aSEnric Balletbò i Serra "bootfile=zImage\0" \ 1186c0a032aSEnric Balletbò i Serra "usbtty=cdc_acm\0" \ 1196c0a032aSEnric Balletbò i Serra "vram=16M\0" \ 120ffe16911SAsh Charles "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ 121ffe16911SAsh Charles "uimageboot=echo Booting from mmc${mmcdev} ...; " \ 12285d17be3SLokesh Vutla "run args_mmc; " \ 123ffe16911SAsh Charles "bootm ${loadaddr}\0" \ 1246c0a032aSEnric Balletbò i Serra "findfdt="\ 1256c0a032aSEnric Balletbò i Serra "if test $board_name = sdp4430; then " \ 1266c0a032aSEnric Balletbò i Serra "setenv fdtfile omap4-sdp.dtb; fi; " \ 1276c0a032aSEnric Balletbò i Serra "if test $board_name = panda; then " \ 1286c0a032aSEnric Balletbò i Serra "setenv fdtfile omap4-panda.dtb; fi;" \ 1296c0a032aSEnric Balletbò i Serra "if test $board_name = panda-a4; then " \ 1306c0a032aSEnric Balletbò i Serra "setenv fdtfile omap4-panda-a4.dtb; fi;" \ 1316c0a032aSEnric Balletbò i Serra "if test $board_name = panda-es; then " \ 1326c0a032aSEnric Balletbò i Serra "setenv fdtfile omap4-panda-es.dtb; fi;" \ 133ffe16911SAsh Charles "if test $board_name = duovero; then " \ 13499907176SAsh Charles "setenv fdtfile omap4-duovero-parlor.dtb; fi;" \ 1356c0a032aSEnric Balletbò i Serra "if test $fdtfile = undefined; then " \ 1366c0a032aSEnric Balletbò i Serra "echo WARNING: Could not determine device tree to use; fi; \0" \ 1372a1a29c5STom Rini BOOTENV 1386c0a032aSEnric Balletbò i Serra 1396c0a032aSEnric Balletbò i Serra /* 1406c0a032aSEnric Balletbò i Serra * Defines for SPL 1416c0a032aSEnric Balletbò i Serra * It is known that this will break HS devices. Since the current size of 1426c0a032aSEnric Balletbò i Serra * SPL is overlapped with public stack and breaking non HS devices to boot. 1436c0a032aSEnric Balletbò i Serra * So moving TEXT_BASE down to non-HS limit. 1446c0a032aSEnric Balletbò i Serra */ 1456c0a032aSEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40300000 146983e3700STom Rini #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 147d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 148d3289aacSTom Rini (128 << 20)) 1496c0a032aSEnric Balletbò i Serra 15070e71b61SEnric Balletbò i Serra #ifdef CONFIG_NAND 15170e71b61SEnric Balletbò i Serra #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ 15270e71b61SEnric Balletbò i Serra #endif 15370e71b61SEnric Balletbò i Serra 1544f80d5baSNishanth Menon #ifdef CONFIG_SPL_BUILD 1554f80d5baSNishanth Menon /* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ 1564f80d5baSNishanth Menon #undef CONFIG_SYS_I2C 1574f80d5baSNishanth Menon #undef CONFIG_SYS_I2C_OMAP24XX 1584f80d5baSNishanth Menon #endif 1594f80d5baSNishanth Menon 1606c0a032aSEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP4_COMMON_H */ 161