xref: /rk3399_rockchip-uboot/include/configs/ti_omap4_common.h (revision 18c534bbfbe9355fc5373547f4f89384a29da516)
16c0a032aSEnric Balletbò i Serra /*
26c0a032aSEnric Balletbò i Serra  * (C) Copyright 2010
36c0a032aSEnric Balletbò i Serra  * Texas Instruments Incorporated.
46c0a032aSEnric Balletbò i Serra  * Aneesh V       <aneesh@ti.com>
56c0a032aSEnric Balletbò i Serra  * Steve Sakoman  <steve@sakoman.com>
66c0a032aSEnric Balletbò i Serra  *
76c0a032aSEnric Balletbò i Serra  * TI OMAP4 common configuration settings
86c0a032aSEnric Balletbò i Serra  *
96c0a032aSEnric Balletbò i Serra  * SPDX-License-Identifier:	GPL-2.0+
106c0a032aSEnric Balletbò i Serra  */
116c0a032aSEnric Balletbò i Serra 
126c0a032aSEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP4_COMMON_H
136c0a032aSEnric Balletbò i Serra #define __CONFIG_TI_OMAP4_COMMON_H
146c0a032aSEnric Balletbò i Serra 
156c0a032aSEnric Balletbò i Serra /*
166c0a032aSEnric Balletbò i Serra  * High Level Configuration Options
176c0a032aSEnric Balletbò i Serra  */
186c0a032aSEnric Balletbò i Serra #define CONFIG_OMAP4430		1	/* which is in a 4430 */
196c0a032aSEnric Balletbò i Serra #define CONFIG_MISC_INIT_R
206c0a032aSEnric Balletbò i Serra #define CONFIG_DISPLAY_CPUINFO		1
216c0a032aSEnric Balletbò i Serra #define CONFIG_DISPLAY_BOARDINFO	1
226c0a032aSEnric Balletbò i Serra 
236c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_THUMB_BUILD
246c0a032aSEnric Balletbò i Serra 
256c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SYS_L2CACHE_OFF
266c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_L2_PL310		1
276c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_PL310_BASE	0x48242000
286c0a032aSEnric Balletbò i Serra #endif
296c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_CACHELINE_SIZE	32
306c0a032aSEnric Balletbò i Serra 
316c0a032aSEnric Balletbò i Serra /* Get CPU defs */
326c0a032aSEnric Balletbò i Serra #include <asm/arch/cpu.h>
336c0a032aSEnric Balletbò i Serra #include <asm/arch/omap.h>
346c0a032aSEnric Balletbò i Serra 
356c0a032aSEnric Balletbò i Serra /* Use General purpose timer 1 */
366c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE		GPT2_BASE
376c0a032aSEnric Balletbò i Serra 
386c0a032aSEnric Balletbò i Serra /*
396c0a032aSEnric Balletbò i Serra  * Total Size Environment - 128k
406c0a032aSEnric Balletbò i Serra  */
416c0a032aSEnric Balletbò i Serra #define CONFIG_ENV_SIZE			(128 << 10)
426c0a032aSEnric Balletbò i Serra 
436c0a032aSEnric Balletbò i Serra /*
446c0a032aSEnric Balletbò i Serra  * For the DDR timing information we can either dynamically determine
456c0a032aSEnric Balletbò i Serra  * the timings to use or use pre-determined timings (based on using the
466c0a032aSEnric Balletbò i Serra  * dynamic method.  Default to the static timing infomation.
476c0a032aSEnric Balletbò i Serra  */
486c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
496c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
506c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
516c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
526c0a032aSEnric Balletbò i Serra #endif
536c0a032aSEnric Balletbò i Serra 
549a0f4004SNishanth Menon #include <configs/ti_armv7_omap.h>
556c0a032aSEnric Balletbò i Serra 
566c0a032aSEnric Balletbò i Serra /*
576c0a032aSEnric Balletbò i Serra  * Hardware drivers
586c0a032aSEnric Balletbò i Serra  */
59c7b9686dSThomas Chou #define CONFIG_SYS_NS16550_CLK		48000000
6053ee6342STom Rini #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
616c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_SERIAL
626c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
636c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM3		UART3_BASE
6453ee6342STom Rini #endif
6553ee6342STom Rini #define CONFIG_CONS_INDEX		3
666c0a032aSEnric Balletbò i Serra 
676c0a032aSEnric Balletbò i Serra /* TWL6030 */
686c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SPL_BUILD
696c0a032aSEnric Balletbò i Serra #define CONFIG_TWL6030_POWER		1
706c0a032aSEnric Balletbò i Serra #endif
716c0a032aSEnric Balletbò i Serra 
726c0a032aSEnric Balletbò i Serra /* USB */
7395de1e2fSPaul Kocialkowski #define CONFIG_USB_MUSB_UDC			1
746c0a032aSEnric Balletbò i Serra #define CONFIG_USB_OMAP3		1
756c0a032aSEnric Balletbò i Serra 
766c0a032aSEnric Balletbò i Serra /* USB device configuration */
776c0a032aSEnric Balletbò i Serra #define CONFIG_USB_DEVICE		1
786c0a032aSEnric Balletbò i Serra #define CONFIG_USB_TTY			1
796c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
806c0a032aSEnric Balletbò i Serra 
816c0a032aSEnric Balletbò i Serra /*
826c0a032aSEnric Balletbò i Serra  * Environment setup
836c0a032aSEnric Balletbò i Serra  */
842a1a29c5STom Rini #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
852a1a29c5STom Rini 	"bootcmd_" #devtypel #instance "=" \
862a1a29c5STom Rini 	"setenv mmcdev " #instance"; "\
872a1a29c5STom Rini 	"setenv bootpart " #instance":2 ; "\
882a1a29c5STom Rini 	"run mmcboot\0"
892a1a29c5STom Rini 
902a1a29c5STom Rini #define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
912a1a29c5STom Rini 	#devtypel #instance " "
922a1a29c5STom Rini 
932a1a29c5STom Rini #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
942a1a29c5STom Rini 	#devtypel #instance " "
952a1a29c5STom Rini 
962a1a29c5STom Rini #define BOOT_TARGET_DEVICES(func) \
972a1a29c5STom Rini 	func(MMC, mmc, 0) \
982a1a29c5STom Rini 	func(LEGACY_MMC, legacy_mmc, 0) \
992a1a29c5STom Rini 	func(MMC, mmc, 1) \
1002a1a29c5STom Rini 	func(LEGACY_MMC, legacy_mmc, 1) \
1012a1a29c5STom Rini 	func(PXE, pxe, na) \
1022a1a29c5STom Rini 	func(DHCP, dhcp, na)
1032a1a29c5STom Rini 
1042a1a29c5STom Rini #define CONFIG_BOOTCOMMAND \
1052a1a29c5STom Rini 	"run findfdt; " \
106*18c534bbSLokesh Vutla 	"run envboot; " \
1072a1a29c5STom Rini 	"run distro_bootcmd"
1082a1a29c5STom Rini 
1092a1a29c5STom Rini #include <config_distro_bootcmd.h>
1102a1a29c5STom Rini 
1116c0a032aSEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \
112fb3ad9bdSTom Rini 	DEFAULT_LINUX_BOOT_ENV \
11385d17be3SLokesh Vutla 	DEFAULT_MMC_TI_ARGS \
1146c0a032aSEnric Balletbò i Serra 	"console=ttyO2,115200n8\0" \
1156c0a032aSEnric Balletbò i Serra 	"fdtfile=undefined\0" \
1166c0a032aSEnric Balletbò i Serra 	"bootpart=0:2\0" \
1176c0a032aSEnric Balletbò i Serra 	"bootdir=/boot\0" \
1186c0a032aSEnric Balletbò i Serra 	"bootfile=zImage\0" \
1196c0a032aSEnric Balletbò i Serra 	"usbtty=cdc_acm\0" \
1206c0a032aSEnric Balletbò i Serra 	"vram=16M\0" \
1216c0a032aSEnric Balletbò i Serra 	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
122ffe16911SAsh Charles 	"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
1236c0a032aSEnric Balletbò i Serra 	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
12485d17be3SLokesh Vutla 		"run args_mmc; " \
1256c0a032aSEnric Balletbò i Serra 		"bootz ${loadaddr} - ${fdtaddr}\0" \
126ffe16911SAsh Charles 	"uimageboot=echo Booting from mmc${mmcdev} ...; " \
12785d17be3SLokesh Vutla 		"run args_mmc; " \
128ffe16911SAsh Charles 		"bootm ${loadaddr}\0" \
1296c0a032aSEnric Balletbò i Serra 	"findfdt="\
1306c0a032aSEnric Balletbò i Serra 		"if test $board_name = sdp4430; then " \
1316c0a032aSEnric Balletbò i Serra 			"setenv fdtfile omap4-sdp.dtb; fi; " \
1326c0a032aSEnric Balletbò i Serra 		"if test $board_name = panda; then " \
1336c0a032aSEnric Balletbò i Serra 			"setenv fdtfile omap4-panda.dtb; fi;" \
1346c0a032aSEnric Balletbò i Serra 		"if test $board_name = panda-a4; then " \
1356c0a032aSEnric Balletbò i Serra 			"setenv fdtfile omap4-panda-a4.dtb; fi;" \
1366c0a032aSEnric Balletbò i Serra 		"if test $board_name = panda-es; then " \
1376c0a032aSEnric Balletbò i Serra 			"setenv fdtfile omap4-panda-es.dtb; fi;" \
138ffe16911SAsh Charles 		"if test $board_name = duovero; then " \
13999907176SAsh Charles 			"setenv fdtfile omap4-duovero-parlor.dtb; fi;" \
1406c0a032aSEnric Balletbò i Serra 		"if test $fdtfile = undefined; then " \
1416c0a032aSEnric Balletbò i Serra 			"echo WARNING: Could not determine device tree to use; fi; \0" \
1426c0a032aSEnric Balletbò i Serra 	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
1432a1a29c5STom Rini 	BOOTENV
1446c0a032aSEnric Balletbò i Serra 
1456c0a032aSEnric Balletbò i Serra /*
1466c0a032aSEnric Balletbò i Serra  * Defines for SPL
1476c0a032aSEnric Balletbò i Serra  * It is known that this will break HS devices. Since the current size of
1486c0a032aSEnric Balletbò i Serra  * SPL is overlapped with public stack and breaking non HS devices to boot.
1496c0a032aSEnric Balletbò i Serra  * So moving TEXT_BASE down to non-HS limit.
1506c0a032aSEnric Balletbò i Serra  */
1516c0a032aSEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE		0x40300000
1526c0a032aSEnric Balletbò i Serra #define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
1536c0a032aSEnric Balletbò i Serra #define CONFIG_SPL_DISPLAY_PRINT
1546c0a032aSEnric Balletbò i Serra #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
155d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
156d3289aacSTom Rini 					 (128 << 20))
1576c0a032aSEnric Balletbò i Serra 
15870e71b61SEnric Balletbò i Serra #ifdef CONFIG_NAND
15970e71b61SEnric Balletbò i Serra #define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
16070e71b61SEnric Balletbò i Serra #endif
16170e71b61SEnric Balletbò i Serra 
1624f80d5baSNishanth Menon #ifdef CONFIG_SPL_BUILD
1634f80d5baSNishanth Menon /* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */
1644f80d5baSNishanth Menon #undef CONFIG_SYS_I2C
1654f80d5baSNishanth Menon #undef CONFIG_SYS_I2C_OMAP24XX
16660c7c30aSPaul Kocialkowski #undef CONFIG_SPL_I2C_SUPPORT
1674f80d5baSNishanth Menon #endif
1684f80d5baSNishanth Menon 
1696c0a032aSEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP4_COMMON_H */
170