xref: /rk3399_rockchip-uboot/include/configs/ti_omap4_common.h (revision 157f8461d468ad7bcd19ad9563b16c824c63bcd4)
16c0a032aSEnric Balletbò i Serra /*
26c0a032aSEnric Balletbò i Serra  * (C) Copyright 2010
36c0a032aSEnric Balletbò i Serra  * Texas Instruments Incorporated.
46c0a032aSEnric Balletbò i Serra  * Aneesh V       <aneesh@ti.com>
56c0a032aSEnric Balletbò i Serra  * Steve Sakoman  <steve@sakoman.com>
66c0a032aSEnric Balletbò i Serra  *
76c0a032aSEnric Balletbò i Serra  * TI OMAP4 common configuration settings
86c0a032aSEnric Balletbò i Serra  *
96c0a032aSEnric Balletbò i Serra  * SPDX-License-Identifier:	GPL-2.0+
106c0a032aSEnric Balletbò i Serra  */
116c0a032aSEnric Balletbò i Serra 
126c0a032aSEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP4_COMMON_H
136c0a032aSEnric Balletbò i Serra #define __CONFIG_TI_OMAP4_COMMON_H
146c0a032aSEnric Balletbò i Serra 
156c0a032aSEnric Balletbò i Serra #define CONFIG_MISC_INIT_R
166c0a032aSEnric Balletbò i Serra 
176c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SYS_L2CACHE_OFF
186c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_L2_PL310		1
196c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_PL310_BASE	0x48242000
206c0a032aSEnric Balletbò i Serra #endif
216c0a032aSEnric Balletbò i Serra 
226c0a032aSEnric Balletbò i Serra /* Get CPU defs */
236c0a032aSEnric Balletbò i Serra #include <asm/arch/cpu.h>
246c0a032aSEnric Balletbò i Serra #include <asm/arch/omap.h>
256c0a032aSEnric Balletbò i Serra 
266c0a032aSEnric Balletbò i Serra /* Use General purpose timer 1 */
276c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE		GPT2_BASE
286c0a032aSEnric Balletbò i Serra 
296c0a032aSEnric Balletbò i Serra /*
306c0a032aSEnric Balletbò i Serra  * Total Size Environment - 128k
316c0a032aSEnric Balletbò i Serra  */
326c0a032aSEnric Balletbò i Serra #define CONFIG_ENV_SIZE			(128 << 10)
336c0a032aSEnric Balletbò i Serra 
346c0a032aSEnric Balletbò i Serra /*
356c0a032aSEnric Balletbò i Serra  * For the DDR timing information we can either dynamically determine
366c0a032aSEnric Balletbò i Serra  * the timings to use or use pre-determined timings (based on using the
376c0a032aSEnric Balletbò i Serra  * dynamic method.  Default to the static timing infomation.
386c0a032aSEnric Balletbò i Serra  */
396c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
406c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
416c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
426c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
436c0a032aSEnric Balletbò i Serra #endif
446c0a032aSEnric Balletbò i Serra 
459a0f4004SNishanth Menon #include <configs/ti_armv7_omap.h>
466c0a032aSEnric Balletbò i Serra 
476c0a032aSEnric Balletbò i Serra /*
486c0a032aSEnric Balletbò i Serra  * Hardware drivers
496c0a032aSEnric Balletbò i Serra  */
50c7b9686dSThomas Chou #define CONFIG_SYS_NS16550_CLK		48000000
5153ee6342STom Rini #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
526c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_SERIAL
536c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
546c0a032aSEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM3		UART3_BASE
5553ee6342STom Rini #endif
5653ee6342STom Rini #define CONFIG_CONS_INDEX		3
576c0a032aSEnric Balletbò i Serra 
586c0a032aSEnric Balletbò i Serra /* TWL6030 */
596c0a032aSEnric Balletbò i Serra #ifndef CONFIG_SPL_BUILD
606c0a032aSEnric Balletbò i Serra #define CONFIG_TWL6030_POWER		1
616c0a032aSEnric Balletbò i Serra #endif
626c0a032aSEnric Balletbò i Serra 
636c0a032aSEnric Balletbò i Serra /* USB */
6495de1e2fSPaul Kocialkowski #define CONFIG_USB_MUSB_UDC			1
656c0a032aSEnric Balletbò i Serra #define CONFIG_USB_OMAP3		1
666c0a032aSEnric Balletbò i Serra 
676c0a032aSEnric Balletbò i Serra /* USB device configuration */
686c0a032aSEnric Balletbò i Serra #define CONFIG_USB_DEVICE		1
696c0a032aSEnric Balletbò i Serra #define CONFIG_USB_TTY			1
706c0a032aSEnric Balletbò i Serra 
716c0a032aSEnric Balletbò i Serra /*
726c0a032aSEnric Balletbò i Serra  * Environment setup
736c0a032aSEnric Balletbò i Serra  */
742a1a29c5STom Rini #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
752a1a29c5STom Rini 	"bootcmd_" #devtypel #instance "=" \
762a1a29c5STom Rini 	"setenv mmcdev " #instance"; "\
772a1a29c5STom Rini 	"setenv bootpart " #instance":2 ; "\
782a1a29c5STom Rini 	"run mmcboot\0"
792a1a29c5STom Rini 
802a1a29c5STom Rini #define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
812a1a29c5STom Rini 	#devtypel #instance " "
822a1a29c5STom Rini 
832a1a29c5STom Rini #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
842a1a29c5STom Rini 	#devtypel #instance " "
852a1a29c5STom Rini 
862a1a29c5STom Rini #define BOOT_TARGET_DEVICES(func) \
872a1a29c5STom Rini 	func(MMC, mmc, 0) \
882a1a29c5STom Rini 	func(LEGACY_MMC, legacy_mmc, 0) \
892a1a29c5STom Rini 	func(MMC, mmc, 1) \
902a1a29c5STom Rini 	func(LEGACY_MMC, legacy_mmc, 1) \
912a1a29c5STom Rini 	func(PXE, pxe, na) \
922a1a29c5STom Rini 	func(DHCP, dhcp, na)
932a1a29c5STom Rini 
942a1a29c5STom Rini #define CONFIG_BOOTCOMMAND \
951e93cc84SLokesh Vutla 	"if test ${boot_fit} -eq 1; then "	\
961e93cc84SLokesh Vutla 		"run update_to_fit;"	\
971e93cc84SLokesh Vutla 	"fi;"	\
982a1a29c5STom Rini 	"run findfdt; " \
9918c534bbSLokesh Vutla 	"run envboot; " \
1002a1a29c5STom Rini 	"run distro_bootcmd"
1012a1a29c5STom Rini 
1022a1a29c5STom Rini #include <config_distro_bootcmd.h>
103*88fdfcd2SSekhar Nori #include <environment/ti/mmc.h>
1042a1a29c5STom Rini 
1056c0a032aSEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \
106fb3ad9bdSTom Rini 	DEFAULT_LINUX_BOOT_ENV \
10785d17be3SLokesh Vutla 	DEFAULT_MMC_TI_ARGS \
1081e93cc84SLokesh Vutla 	DEFAULT_FIT_TI_ARGS \
1096c0a032aSEnric Balletbò i Serra 	"console=ttyO2,115200n8\0" \
1106c0a032aSEnric Balletbò i Serra 	"fdtfile=undefined\0" \
1116c0a032aSEnric Balletbò i Serra 	"bootpart=0:2\0" \
1126c0a032aSEnric Balletbò i Serra 	"bootdir=/boot\0" \
1136c0a032aSEnric Balletbò i Serra 	"bootfile=zImage\0" \
1146c0a032aSEnric Balletbò i Serra 	"usbtty=cdc_acm\0" \
1156c0a032aSEnric Balletbò i Serra 	"vram=16M\0" \
116ffe16911SAsh Charles 	"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
117ffe16911SAsh Charles 	"uimageboot=echo Booting from mmc${mmcdev} ...; " \
11885d17be3SLokesh Vutla 		"run args_mmc; " \
119ffe16911SAsh Charles 		"bootm ${loadaddr}\0" \
1206c0a032aSEnric Balletbò i Serra 	"findfdt="\
1216c0a032aSEnric Balletbò i Serra 		"if test $board_name = sdp4430; then " \
1226c0a032aSEnric Balletbò i Serra 			"setenv fdtfile omap4-sdp.dtb; fi; " \
1236c0a032aSEnric Balletbò i Serra 		"if test $board_name = panda; then " \
1246c0a032aSEnric Balletbò i Serra 			"setenv fdtfile omap4-panda.dtb; fi;" \
1256c0a032aSEnric Balletbò i Serra 		"if test $board_name = panda-a4; then " \
1266c0a032aSEnric Balletbò i Serra 			"setenv fdtfile omap4-panda-a4.dtb; fi;" \
1276c0a032aSEnric Balletbò i Serra 		"if test $board_name = panda-es; then " \
1286c0a032aSEnric Balletbò i Serra 			"setenv fdtfile omap4-panda-es.dtb; fi;" \
129ffe16911SAsh Charles 		"if test $board_name = duovero; then " \
13099907176SAsh Charles 			"setenv fdtfile omap4-duovero-parlor.dtb; fi;" \
1316c0a032aSEnric Balletbò i Serra 		"if test $fdtfile = undefined; then " \
1326c0a032aSEnric Balletbò i Serra 			"echo WARNING: Could not determine device tree to use; fi; \0" \
1332a1a29c5STom Rini 	BOOTENV
1346c0a032aSEnric Balletbò i Serra 
1356c0a032aSEnric Balletbò i Serra /*
1366c0a032aSEnric Balletbò i Serra  * Defines for SPL
1376c0a032aSEnric Balletbò i Serra  * It is known that this will break HS devices. Since the current size of
1386c0a032aSEnric Balletbò i Serra  * SPL is overlapped with public stack and breaking non HS devices to boot.
1396c0a032aSEnric Balletbò i Serra  * So moving TEXT_BASE down to non-HS limit.
1406c0a032aSEnric Balletbò i Serra  */
1416c0a032aSEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE		0x40300000
142d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
143d3289aacSTom Rini 					 (128 << 20))
1446c0a032aSEnric Balletbò i Serra 
1454f80d5baSNishanth Menon #ifdef CONFIG_SPL_BUILD
1464f80d5baSNishanth Menon /* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */
1474f80d5baSNishanth Menon #undef CONFIG_SYS_I2C
1484f80d5baSNishanth Menon #endif
1494f80d5baSNishanth Menon 
1506c0a032aSEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP4_COMMON_H */
151