1*9a0f4004SNishanth Menon /* 2*9a0f4004SNishanth Menon * ti_armv7_omap.h 3*9a0f4004SNishanth Menon * 4*9a0f4004SNishanth Menon * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ 5*9a0f4004SNishanth Menon * 6*9a0f4004SNishanth Menon * SPDX-License-Identifier: GPL-2.0+ 7*9a0f4004SNishanth Menon * 8*9a0f4004SNishanth Menon * The various ARMv7 SoCs from TI all share a number of IP blocks when 9*9a0f4004SNishanth Menon * implementing a given feature. This is meant to isolate the features 10*9a0f4004SNishanth Menon * that are based on OMAP architecture. 11*9a0f4004SNishanth Menon */ 12*9a0f4004SNishanth Menon #ifndef __CONFIG_TI_ARMV7_OMAP_H__ 13*9a0f4004SNishanth Menon #define __CONFIG_TI_ARMV7_OMAP_H__ 14*9a0f4004SNishanth Menon 15*9a0f4004SNishanth Menon /* I2C IP block */ 16*9a0f4004SNishanth Menon #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 17*9a0f4004SNishanth Menon #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 18*9a0f4004SNishanth Menon 19*9a0f4004SNishanth Menon /* 20*9a0f4004SNishanth Menon * GPMC NAND block. We support 1 device and the physical address to 21*9a0f4004SNishanth Menon * access CS0 at is 0x8000000. 22*9a0f4004SNishanth Menon */ 23*9a0f4004SNishanth Menon #ifdef CONFIG_NAND 24*9a0f4004SNishanth Menon #ifndef CONFIG_SYS_NAND_BASE 25*9a0f4004SNishanth Menon #define CONFIG_SYS_NAND_BASE 0x8000000 26*9a0f4004SNishanth Menon #endif 27*9a0f4004SNishanth Menon #define CONFIG_SYS_MAX_NAND_DEVICE 1 28*9a0f4004SNishanth Menon #endif 29*9a0f4004SNishanth Menon 30*9a0f4004SNishanth Menon /* Now for the remaining common defines */ 31*9a0f4004SNishanth Menon #include <configs/ti_armv7_common.h> 32*9a0f4004SNishanth Menon 33*9a0f4004SNishanth Menon #endif /* __CONFIG_TI_ARMV7_OMAP_H__ */ 34