1 /* 2 * ti816x_evm.h 3 * 4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 5 * Antoine Tenart, <atenart@adeneo-embedded.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_TI816X_EVM_H 11 #define __CONFIG_TI816X_EVM_H 12 13 #define CONFIG_TI81XX 14 #define CONFIG_TI816X 15 16 #define CONFIG_ARCH_CPU_INIT 17 18 #include <asm/arch/omap.h> 19 20 #define CONFIG_ENV_SIZE 0x2000 21 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) 22 #define CONFIG_SYS_LONGHELP /* undef save memory */ 23 #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM 24 25 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 26 #define CONFIG_SETUP_MEMORY_TAGS 27 #define CONFIG_INITRD_TAG /* required for ramdisk support */ 28 29 #define CONFIG_EXTRA_ENV_SETTINGS \ 30 "loadaddr=0x81000000\0" \ 31 32 #define CONFIG_BOOTCOMMAND \ 33 "mmc rescan;" \ 34 "fatload mmc 0 ${loadaddr} uImage;" \ 35 "bootm ${loadaddr}" \ 36 37 #define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk" 38 39 /* Clock Defines */ 40 #define V_OSCK 24000000 /* Clock output from T2 */ 41 #define V_SCLK (V_OSCK >> 1) 42 43 #define CONFIG_SYS_MAXARGS 32 44 #define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ 45 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 46 + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ 47 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ 48 49 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ 50 51 #define CONFIG_CMD_ASKENV 52 #define CONFIG_OMAP_GPIO 53 54 #define CONFIG_FS_FAT 55 56 /* 57 * Only one of the following two options (DDR3/DDR2) should be enabled 58 * CONFIG_TI816X_EVM_DDR2 59 * CONFIG_TI816X_EVM_DDR3 60 */ 61 #define CONFIG_TI816X_EVM_DDR3 62 63 /* 64 * Supported values: 400, 531, 675 or 796 MHz 65 */ 66 #define CONFIG_TI816X_DDR_PLL_796 67 68 #define CONFIG_TI816X_USE_EMIF0 1 69 #define CONFIG_TI816X_USE_EMIF1 1 70 71 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ 72 #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ 73 #define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ 74 #define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ 75 #define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */ 76 77 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ 78 #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 79 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 80 GENERATED_GBL_DATA_SIZE) 81 82 /** 83 * Platform/Board specific defs 84 */ 85 #define CONFIG_SYS_CLK_FREQ 27000000 86 #define CONFIG_SYS_TIMERBASE 0x4802E000 87 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 88 89 #undef CONFIG_NAND_OMAP_GPMC 90 91 /* 92 * NS16550 Configuration 93 */ 94 #define CONFIG_SYS_NS16550_SERIAL 95 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 96 #define CONFIG_SYS_NS16550_CLK (48000000) 97 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ 98 99 /* allow overwriting serial config and ethaddr */ 100 #define CONFIG_ENV_OVERWRITE 101 102 #define CONFIG_SERIAL1 103 #define CONFIG_SERIAL2 104 #define CONFIG_SERIAL3 105 #define CONFIG_CONS_INDEX 1 106 107 #define CONFIG_ENV_IS_NOWHERE 108 109 /* SPL */ 110 /* Defines for SPL */ 111 #define CONFIG_SPL_FRAMEWORK 112 #define CONFIG_SPL_TEXT_BASE 0x40400000 113 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 114 CONFIG_SPL_TEXT_BASE) 115 116 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 117 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 118 119 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 120 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 121 122 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 123 #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 124 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 125 126 #define CONFIG_SPL_BOARD_INIT 127 128 #define CONFIG_SYS_TEXT_BASE 0x80800000 129 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 130 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 131 132 /* Since SPL did pll and ddr initialization for us, 133 * we don't need to do it twice. 134 */ 135 #ifndef CONFIG_SPL_BUILD 136 #define CONFIG_SKIP_LOWLEVEL_INIT 137 #endif 138 139 #endif 140