1 /* 2 * ti816x_evm.h 3 * 4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 5 * Antoine Tenart, <atenart@adeneo-embedded.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_TI816X_EVM_H 11 #define __CONFIG_TI816X_EVM_H 12 13 #define CONFIG_TI81XX 14 #define CONFIG_TI816X 15 16 #include <configs/ti_armv7_omap.h> 17 #include <asm/arch/omap.h> 18 19 #define CONFIG_ENV_SIZE 0x2000 20 #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM 21 22 #define CONFIG_EXTRA_ENV_SETTINGS \ 23 DEFAULT_LINUX_BOOT_ENV \ 24 "mtdids=" MTDIDS_DEFAULT "\0" \ 25 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 26 27 #define CONFIG_BOOTCOMMAND \ 28 "mmc rescan;" \ 29 "fatload mmc 0 ${loadaddr} uImage;" \ 30 "bootm ${loadaddr}" \ 31 32 #define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk" 33 34 /* Clock Defines */ 35 #define V_OSCK 24000000 /* Clock output from T2 */ 36 #define V_SCLK (V_OSCK >> 1) 37 38 #define CONFIG_CMD_ASKENV 39 40 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ 41 #define CONFIG_SYS_SDRAM_BASE 0x80000000 42 43 /** 44 * Platform/Board specific defs 45 */ 46 #define CONFIG_SYS_CLK_FREQ 27000000 47 #define CONFIG_SYS_TIMERBASE 0x4802E000 48 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 49 50 /* 51 * NS16550 Configuration 52 */ 53 #define CONFIG_SYS_NS16550_SERIAL 54 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 55 #define CONFIG_SYS_NS16550_CLK (48000000) 56 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ 57 58 /* allow overwriting serial config and ethaddr */ 59 #define CONFIG_ENV_OVERWRITE 60 61 #define CONFIG_SERIAL1 62 #define CONFIG_SERIAL2 63 #define CONFIG_SERIAL3 64 #define CONFIG_CONS_INDEX 1 65 66 /* 67 * GPMC NAND block. We support 1 device and the physical address to 68 * access CS0 at is 0x8000000. 69 */ 70 #define CONFIG_SYS_NAND_BASE 0x8000000 71 #define CONFIG_SYS_MAX_NAND_DEVICE 1 72 73 /* NAND: SPL related configs */ 74 #define CONFIG_SPL_NAND_AM33XX_BCH 75 76 /* NAND: device related configs */ 77 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 78 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 79 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 80 CONFIG_SYS_NAND_PAGE_SIZE) 81 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 82 #define CONFIG_SYS_NAND_OOBSIZE 64 83 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 84 /* NAND: driver related configs */ 85 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 86 #define CONFIG_NAND_OMAP_ELM 87 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 88 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 89 10, 11, 12, 13, 14, 15, 16, 17, \ 90 18, 19, 20, 21, 22, 23, 24, 25, \ 91 26, 27, 28, 29, 30, 31, 32, 33, \ 92 34, 35, 36, 37, 38, 39, 40, 41, \ 93 42, 43, 44, 45, 46, 47, 48, 49, \ 94 50, 51, 52, 53, 54, 55, 56, 57, } 95 96 #define CONFIG_SYS_NAND_ECCSIZE 512 97 #define CONFIG_SYS_NAND_ECCBYTES 14 98 #define CONFIG_SYS_NAND_ONFI_DETECTION 99 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 100 #define MTDIDS_DEFAULT "nand0=nand.0" 101 #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ 102 "128k(NAND.SPL)," \ 103 "128k(NAND.SPL.backup1)," \ 104 "128k(NAND.SPL.backup2)," \ 105 "128k(NAND.SPL.backup3)," \ 106 "256k(NAND.u-boot-spl-os)," \ 107 "1m(NAND.u-boot)," \ 108 "128k(NAND.u-boot-env)," \ 109 "128k(NAND.u-boot-env.backup1)," \ 110 "8m(NAND.kernel)," \ 111 "-(NAND.file-system)" 112 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 113 #define CONFIG_ENV_IS_IN_NAND 114 #define CONFIG_ENV_OFFSET 0x001c0000 115 #define CONFIG_ENV_OFFSET_REDUND 0x001e0000 116 #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 117 118 /* SPL */ 119 /* Defines for SPL */ 120 #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ 121 #define CONFIG_SPL_TEXT_BASE 0x40400000 122 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 123 CONFIG_SPL_TEXT_BASE) 124 125 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 126 127 #define CONFIG_SYS_TEXT_BASE 0x80800000 128 129 /* Since SPL did pll and ddr initialization for us, 130 * we don't need to do it twice. 131 */ 132 #ifndef CONFIG_SPL_BUILD 133 #define CONFIG_SKIP_LOWLEVEL_INIT 134 #endif 135 136 /* 137 * Disable MMC DM for SPL build and can be re-enabled after adding 138 * DM support in SPL 139 */ 140 #ifdef CONFIG_SPL_BUILD 141 #undef CONFIG_DM_MMC 142 #undef CONFIG_TIMER 143 #undef CONFIG_DM_USB 144 #endif 145 #endif 146