1425faf74STENART Antoine /* 2425faf74STENART Antoine * ti816x_evm.h 3425faf74STENART Antoine * 4425faf74STENART Antoine * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 5425faf74STENART Antoine * Antoine Tenart, <atenart@adeneo-embedded.com> 6425faf74STENART Antoine * 7425faf74STENART Antoine * SPDX-License-Identifier: GPL-2.0+ 8425faf74STENART Antoine */ 9425faf74STENART Antoine 10425faf74STENART Antoine #ifndef __CONFIG_TI816X_EVM_H 11425faf74STENART Antoine #define __CONFIG_TI816X_EVM_H 12425faf74STENART Antoine 13425faf74STENART Antoine #define CONFIG_TI81XX 14425faf74STENART Antoine #define CONFIG_TI816X 15425faf74STENART Antoine #define CONFIG_SYS_NO_FLASH 16425faf74STENART Antoine #define CONFIG_OMAP 17425faf74STENART Antoine #define CONFIG_OMAP_COMMON 18425faf74STENART Antoine 19425faf74STENART Antoine #define CONFIG_ARCH_CPU_INIT 20425faf74STENART Antoine 21425faf74STENART Antoine #include <asm/arch/omap.h> 22425faf74STENART Antoine 23425faf74STENART Antoine #define CONFIG_ENV_SIZE 0x2000 24425faf74STENART Antoine #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) 25425faf74STENART Antoine #define CONFIG_SYS_LONGHELP /* undef save memory */ 26425faf74STENART Antoine #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM 27425faf74STENART Antoine 28425faf74STENART Antoine #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 29425faf74STENART Antoine #define CONFIG_SETUP_MEMORY_TAGS 30425faf74STENART Antoine #define CONFIG_INITRD_TAG /* required for ramdisk support */ 31425faf74STENART Antoine 32425faf74STENART Antoine #define CONFIG_EXTRA_ENV_SETTINGS \ 33425faf74STENART Antoine "loadaddr=0x81000000\0" \ 34425faf74STENART Antoine 35425faf74STENART Antoine #define CONFIG_BOOTCOMMAND \ 36425faf74STENART Antoine "mmc rescan;" \ 37425faf74STENART Antoine "fatload mmc 0 ${loadaddr} uImage;" \ 38425faf74STENART Antoine "bootm ${loadaddr}" \ 39425faf74STENART Antoine 40425faf74STENART Antoine #define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk" 41425faf74STENART Antoine 42425faf74STENART Antoine /* Clock Defines */ 43425faf74STENART Antoine #define V_OSCK 24000000 /* Clock output from T2 */ 44425faf74STENART Antoine #define V_SCLK (V_OSCK >> 1) 45425faf74STENART Antoine 46425faf74STENART Antoine #define CONFIG_SYS_MAXARGS 32 47425faf74STENART Antoine #define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ 48425faf74STENART Antoine #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 49425faf74STENART Antoine + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ 50425faf74STENART Antoine #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ 51425faf74STENART Antoine 52425faf74STENART Antoine #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ 53425faf74STENART Antoine 54425faf74STENART Antoine #define CONFIG_CMD_ASKEN 55425faf74STENART Antoine #define CONFIG_OMAP_GPIO 56425faf74STENART Antoine #define CONFIG_MMC 57425faf74STENART Antoine #define CONFIG_GENERIC_MMC 58425faf74STENART Antoine #define CONFIG_OMAP_HSMMC 59425faf74STENART Antoine #define CONFIG_DOS_PARTITION 60425faf74STENART Antoine 61425faf74STENART Antoine #define CONFIG_FS_FAT 62425faf74STENART Antoine 63425faf74STENART Antoine /* 64425faf74STENART Antoine * Only one of the following two options (DDR3/DDR2) should be enabled 65425faf74STENART Antoine * CONFIG_TI816X_EVM_DDR2 66425faf74STENART Antoine * CONFIG_TI816X_EVM_DDR3 67425faf74STENART Antoine */ 68425faf74STENART Antoine #define CONFIG_TI816X_EVM_DDR3 69425faf74STENART Antoine 70425faf74STENART Antoine /* 71425faf74STENART Antoine * Supported values: 400, 531, 675 or 796 MHz 72425faf74STENART Antoine */ 73425faf74STENART Antoine #define CONFIG_TI816X_DDR_PLL_796 74425faf74STENART Antoine 75425faf74STENART Antoine #define CONFIG_TI816X_USE_EMIF0 1 76425faf74STENART Antoine #define CONFIG_TI816X_USE_EMIF1 1 77425faf74STENART Antoine 78425faf74STENART Antoine #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ 79425faf74STENART Antoine #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ 80425faf74STENART Antoine #define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ 81425faf74STENART Antoine #define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ 82425faf74STENART Antoine #define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */ 83425faf74STENART Antoine 84425faf74STENART Antoine #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ 85425faf74STENART Antoine #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 86425faf74STENART Antoine #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 87425faf74STENART Antoine GENERATED_GBL_DATA_SIZE) 88425faf74STENART Antoine 89425faf74STENART Antoine /** 90425faf74STENART Antoine * Platform/Board specific defs 91425faf74STENART Antoine */ 92425faf74STENART Antoine #define CONFIG_SYS_CLK_FREQ 27000000 93425faf74STENART Antoine #define CONFIG_SYS_TIMERBASE 0x4802E000 94425faf74STENART Antoine #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 95425faf74STENART Antoine 96425faf74STENART Antoine #undef CONFIG_NAND_OMAP_GPMC 97425faf74STENART Antoine 98425faf74STENART Antoine /* 99425faf74STENART Antoine * NS16550 Configuration 100425faf74STENART Antoine */ 101425faf74STENART Antoine #define CONFIG_SYS_NS16550_SERIAL 102425faf74STENART Antoine #define CONFIG_SYS_NS16550_REG_SIZE (-4) 103425faf74STENART Antoine #define CONFIG_SYS_NS16550_CLK (48000000) 104425faf74STENART Antoine #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ 105425faf74STENART Antoine 106425faf74STENART Antoine #define CONFIG_BAUDRATE 115200 107425faf74STENART Antoine 108425faf74STENART Antoine /* allow overwriting serial config and ethaddr */ 109425faf74STENART Antoine #define CONFIG_ENV_OVERWRITE 110425faf74STENART Antoine 111425faf74STENART Antoine #define CONFIG_SERIAL1 112425faf74STENART Antoine #define CONFIG_SERIAL2 113425faf74STENART Antoine #define CONFIG_SERIAL3 114425faf74STENART Antoine #define CONFIG_CONS_INDEX 1 115425faf74STENART Antoine 116425faf74STENART Antoine #define CONFIG_ENV_IS_NOWHERE 117425faf74STENART Antoine 118425faf74STENART Antoine /* SPL */ 119425faf74STENART Antoine /* Defines for SPL */ 120425faf74STENART Antoine #define CONFIG_SPL_FRAMEWORK 121425faf74STENART Antoine #define CONFIG_SPL_TEXT_BASE 0x40400000 122fa2f81b0STom Rini #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 123fa2f81b0STom Rini CONFIG_SPL_TEXT_BASE) 124425faf74STENART Antoine 125425faf74STENART Antoine #define CONFIG_SPL_BSS_START_ADDR 0x80000000 126425faf74STENART Antoine #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 127425faf74STENART Antoine 128e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 129205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 130425faf74STENART Antoine 131425faf74STENART Antoine #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 132425faf74STENART Antoine #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 133*983e3700STom Rini #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 134425faf74STENART Antoine 135425faf74STENART Antoine #define CONFIG_SPL_BOARD_INIT 136425faf74STENART Antoine 137425faf74STENART Antoine #define CONFIG_SYS_TEXT_BASE 0x80800000 138425faf74STENART Antoine #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 139425faf74STENART Antoine #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 140425faf74STENART Antoine 141425faf74STENART Antoine /* Since SPL did pll and ddr initialization for us, 142425faf74STENART Antoine * we don't need to do it twice. 143425faf74STENART Antoine */ 144425faf74STENART Antoine #ifndef CONFIG_SPL_BUILD 145425faf74STENART Antoine #define CONFIG_SKIP_LOWLEVEL_INIT 146425faf74STENART Antoine #endif 147425faf74STENART Antoine 148425faf74STENART Antoine /* Unsupported features */ 149425faf74STENART Antoine #undef CONFIG_USE_IRQ 150425faf74STENART Antoine 151425faf74STENART Antoine #endif 152