1 /* 2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_THEADORABLE_H 8 #define _CONFIG_THEADORABLE_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 /* 16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17 * for DDR ECC byte filling in the SPL before loading the main 18 * U-Boot into it. 19 */ 20 #define CONFIG_SYS_TEXT_BASE 0x00800000 21 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22 23 /* 24 * Commands configuration 25 */ 26 #define CONFIG_CMD_BOOTZ 27 #define CONFIG_CMD_CACHE 28 #define CONFIG_CMD_ENV 29 #define CONFIG_CMD_EXT2 30 #define CONFIG_CMD_EXT4 31 #define CONFIG_CMD_FAT 32 #define CONFIG_CMD_FS_GENERIC 33 #define CONFIG_CMD_SATA 34 35 /* 36 * The debugging version enables USB support via defconfig. 37 * This version should also enable all other non-production 38 * interfaces / features. 39 */ 40 #ifdef CONFIG_USB 41 #define CONFIG_CMD_PCI 42 #endif 43 44 /* I2C */ 45 #define CONFIG_SYS_I2C 46 #define CONFIG_SYS_I2C_MVTWSI 47 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 48 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE 49 #define CONFIG_SYS_I2C_SLAVE 0x0 50 #define CONFIG_SYS_I2C_SPEED 100000 51 52 /* USB/EHCI configuration */ 53 #define CONFIG_EHCI_IS_TDI 54 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 55 56 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 57 58 /* SPI NOR flash default params, used by sf commands */ 59 #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */ 60 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 61 62 /* Environment in SPI NOR flash */ 63 #define CONFIG_ENV_IS_IN_SPI_FLASH 64 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 65 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 66 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 67 #define CONFIG_ENV_OVERWRITE 68 69 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 70 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 71 72 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 73 #define CONFIG_SYS_ALT_MEMTEST 74 #define CONFIG_PREBOOT 75 76 /* Keep device tree and initrd in lower memory so the kernel can access them */ 77 #define CONFIG_EXTRA_ENV_SETTINGS \ 78 "fdt_high=0x10000000\0" \ 79 "initrd_high=0x10000000\0" 80 81 /* SATA support */ 82 #define CONFIG_SYS_SATA_MAX_DEVICE 1 83 #define CONFIG_SATA_MV 84 #define CONFIG_LIBATA 85 #define CONFIG_LBA48 86 #define CONFIG_EFI_PARTITION 87 #define CONFIG_DOS_PARTITION 88 89 /* Additional FS support/configuration */ 90 #define CONFIG_SUPPORT_VFAT 91 92 /* PCIe support */ 93 #ifdef CONFIG_CMD_PCI 94 #ifndef CONFIG_SPL_BUILD 95 #define CONFIG_PCI 96 #define CONFIG_PCI_MVEBU 97 #define CONFIG_PCI_PNP 98 #define CONFIG_BOARD_LATE_INIT /* for PEX switch test */ 99 #endif 100 #endif 101 102 /* Enable LCD and reserve 512KB from top of memory*/ 103 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000 104 105 #define CONFIG_VIDEO 106 #define CONFIG_CFB_CONSOLE 107 #define CONFIG_VGA_AS_SINGLE_DEVICE 108 #define CONFIG_CMD_BMP 109 110 /* FPGA programming support */ 111 #define CONFIG_FPGA 112 #define CONFIG_FPGA_ALTERA 113 #define CONFIG_FPGA_STRATIX_V 114 115 /* 116 * Bootcounter 117 */ 118 #define CONFIG_BOOTCOUNT_LIMIT 119 #define CONFIG_BOOTCOUNT_RAM 120 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ 121 #define BOOTCOUNT_ADDR 0x1000 122 123 /* 124 * mv-common.h should be defined after CMD configs since it used them 125 * to enable certain macros 126 */ 127 #include "mv-common.h" 128 129 /* 130 * Memory layout while starting into the bin_hdr via the 131 * BootROM: 132 * 133 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 134 * 0x4000.4030 bin_hdr start address 135 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 136 * 0x4007.fffc BootROM stack top 137 * 138 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 139 * L2 cache thus cannot be used. 140 */ 141 142 /* SPL */ 143 /* Defines for SPL */ 144 #define CONFIG_SPL_FRAMEWORK 145 #define CONFIG_SPL_TEXT_BASE 0x40004030 146 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 147 148 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 149 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 150 151 #ifdef CONFIG_SPL_BUILD 152 #define CONFIG_SYS_MALLOC_SIMPLE 153 #endif 154 155 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 156 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 157 158 #define CONFIG_SPL_LIBCOMMON_SUPPORT 159 #define CONFIG_SPL_LIBGENERIC_SUPPORT 160 #define CONFIG_SPL_SERIAL_SUPPORT 161 #define CONFIG_SPL_I2C_SUPPORT 162 163 /* SPL related SPI defines */ 164 #define CONFIG_SPL_SPI_SUPPORT 165 #define CONFIG_SPL_SPI_FLASH_SUPPORT 166 #define CONFIG_SPL_SPI_LOAD 167 #define CONFIG_SPL_SPI_BUS 0 168 #define CONFIG_SPL_SPI_CS 0 169 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 170 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 171 172 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 173 #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ 174 175 #endif /* _CONFIG_THEADORABLE_H */ 176