1b20c38a9SStefan Roese /* 2b20c38a9SStefan Roese * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 3b20c38a9SStefan Roese * 4b20c38a9SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5b20c38a9SStefan Roese */ 6b20c38a9SStefan Roese 7b20c38a9SStefan Roese #ifndef _CONFIG_THEADORABLE_H 8b20c38a9SStefan Roese #define _CONFIG_THEADORABLE_H 9b20c38a9SStefan Roese 10b20c38a9SStefan Roese /* 11b20c38a9SStefan Roese * High Level Configuration Options (easy to change) 12b20c38a9SStefan Roese */ 13b20c38a9SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 14b20c38a9SStefan Roese 15b20c38a9SStefan Roese /* 16b20c38a9SStefan Roese * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17b20c38a9SStefan Roese * for DDR ECC byte filling in the SPL before loading the main 18b20c38a9SStefan Roese * U-Boot into it. 19b20c38a9SStefan Roese */ 20b20c38a9SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00800000 21b20c38a9SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22b20c38a9SStefan Roese 23b20c38a9SStefan Roese /* 24b20c38a9SStefan Roese * Commands configuration 25b20c38a9SStefan Roese */ 26b20c38a9SStefan Roese #define CONFIG_CMD_BOOTZ 27b20c38a9SStefan Roese #define CONFIG_CMD_CACHE 28b20c38a9SStefan Roese #define CONFIG_CMD_ENV 29b20c38a9SStefan Roese #define CONFIG_CMD_EXT2 30b20c38a9SStefan Roese #define CONFIG_CMD_EXT4 31b20c38a9SStefan Roese #define CONFIG_CMD_FAT 32b20c38a9SStefan Roese #define CONFIG_CMD_FS_GENERIC 33b20c38a9SStefan Roese #define CONFIG_CMD_I2C 34b20c38a9SStefan Roese #define CONFIG_CMD_SATA 35b20c38a9SStefan Roese #define CONFIG_CMD_TIME 36b20c38a9SStefan Roese 37b20c38a9SStefan Roese /* 38b20c38a9SStefan Roese * The debugging version enables USB support via defconfig. 39b20c38a9SStefan Roese * This version should also enable all other non-production 40b20c38a9SStefan Roese * interfaces / features. 41b20c38a9SStefan Roese */ 42b20c38a9SStefan Roese #ifdef CONFIG_USB 43b20c38a9SStefan Roese #define CONFIG_CMD_DHCP 44b20c38a9SStefan Roese #define CONFIG_CMD_PCI 45b20c38a9SStefan Roese #define CONFIG_CMD_PING 46b20c38a9SStefan Roese #define CONFIG_CMD_SPI 47b20c38a9SStefan Roese #define CONFIG_CMD_TFTPPUT 48b20c38a9SStefan Roese #endif 49b20c38a9SStefan Roese 50b20c38a9SStefan Roese /* I2C */ 51b20c38a9SStefan Roese #define CONFIG_SYS_I2C 52b20c38a9SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 53b20c38a9SStefan Roese #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 54b20c38a9SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 55b20c38a9SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 56b20c38a9SStefan Roese 57b20c38a9SStefan Roese /* USB/EHCI configuration */ 58b20c38a9SStefan Roese #define CONFIG_EHCI_IS_TDI 59b20c38a9SStefan Roese #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 60b20c38a9SStefan Roese 61b20c38a9SStefan Roese #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 62b20c38a9SStefan Roese 63b20c38a9SStefan Roese /* SPI NOR flash default params, used by sf commands */ 64b20c38a9SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */ 65b20c38a9SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 66b20c38a9SStefan Roese 67b20c38a9SStefan Roese /* Environment in SPI NOR flash */ 68b20c38a9SStefan Roese #define CONFIG_ENV_IS_IN_SPI_FLASH 69b20c38a9SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 70b20c38a9SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 71b20c38a9SStefan Roese #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 72b20c38a9SStefan Roese #define CONFIG_ENV_OVERWRITE 73b20c38a9SStefan Roese 74b20c38a9SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 75b20c38a9SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 76b20c38a9SStefan Roese 77b20c38a9SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 78b20c38a9SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 79b20c38a9SStefan Roese #define CONFIG_PREBOOT 80b20c38a9SStefan Roese 81b20c38a9SStefan Roese #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 82b20c38a9SStefan Roese #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 83b20c38a9SStefan Roese 84b20c38a9SStefan Roese /* Keep device tree and initrd in lower memory so the kernel can access them */ 85b20c38a9SStefan Roese #define CONFIG_EXTRA_ENV_SETTINGS \ 86b20c38a9SStefan Roese "fdt_high=0x10000000\0" \ 87b20c38a9SStefan Roese "initrd_high=0x10000000\0" 88b20c38a9SStefan Roese 89b20c38a9SStefan Roese /* SATA support */ 90b20c38a9SStefan Roese #define CONFIG_SYS_SATA_MAX_DEVICE 1 91b20c38a9SStefan Roese #define CONFIG_SATA_MV 92b20c38a9SStefan Roese #define CONFIG_LIBATA 93b20c38a9SStefan Roese #define CONFIG_LBA48 94b20c38a9SStefan Roese #define CONFIG_EFI_PARTITION 95b20c38a9SStefan Roese #define CONFIG_DOS_PARTITION 96b20c38a9SStefan Roese 97b20c38a9SStefan Roese /* Additional FS support/configuration */ 98b20c38a9SStefan Roese #define CONFIG_SUPPORT_VFAT 99b20c38a9SStefan Roese 100b20c38a9SStefan Roese /* PCIe support */ 101b20c38a9SStefan Roese #ifdef CONFIG_CMD_PCI 102b20c38a9SStefan Roese #ifndef CONFIG_SPL_BUILD 103b20c38a9SStefan Roese #define CONFIG_PCI 104b20c38a9SStefan Roese #define CONFIG_PCI_MVEBU 105b20c38a9SStefan Roese #define CONFIG_PCI_PNP 106b20c38a9SStefan Roese #endif 107b20c38a9SStefan Roese #endif 108b20c38a9SStefan Roese 109b20c38a9SStefan Roese /* Enable LCD and reserve 512KB from top of memory*/ 110b20c38a9SStefan Roese #define CONFIG_SYS_MEM_TOP_HIDE 0x80000 111b20c38a9SStefan Roese 112b20c38a9SStefan Roese #define CONFIG_VIDEO 113b20c38a9SStefan Roese #define CONFIG_CFB_CONSOLE 114b20c38a9SStefan Roese #define CONFIG_VGA_AS_SINGLE_DEVICE 115b20c38a9SStefan Roese #define CONFIG_CMD_BMP 116b20c38a9SStefan Roese 117*aea02abeSStefan Roese /* FPGA programming support */ 118*aea02abeSStefan Roese #define CONFIG_FPGA 119*aea02abeSStefan Roese #define CONFIG_FPGA_ALTERA 120*aea02abeSStefan Roese #define CONFIG_FPGA_STRATIX_V 121*aea02abeSStefan Roese 122b20c38a9SStefan Roese /* 123b20c38a9SStefan Roese * mv-common.h should be defined after CMD configs since it used them 124b20c38a9SStefan Roese * to enable certain macros 125b20c38a9SStefan Roese */ 126b20c38a9SStefan Roese #include "mv-common.h" 127b20c38a9SStefan Roese 128b20c38a9SStefan Roese /* 129b20c38a9SStefan Roese * Memory layout while starting into the bin_hdr via the 130b20c38a9SStefan Roese * BootROM: 131b20c38a9SStefan Roese * 132b20c38a9SStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 133b20c38a9SStefan Roese * 0x4000.4030 bin_hdr start address 134b20c38a9SStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 135b20c38a9SStefan Roese * 0x4007.fffc BootROM stack top 136b20c38a9SStefan Roese * 137b20c38a9SStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 138b20c38a9SStefan Roese * L2 cache thus cannot be used. 139b20c38a9SStefan Roese */ 140b20c38a9SStefan Roese 141b20c38a9SStefan Roese /* SPL */ 142b20c38a9SStefan Roese /* Defines for SPL */ 143b20c38a9SStefan Roese #define CONFIG_SPL_FRAMEWORK 144b20c38a9SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 145b20c38a9SStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 146b20c38a9SStefan Roese 147b20c38a9SStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 148b20c38a9SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 149b20c38a9SStefan Roese 150b20c38a9SStefan Roese #ifdef CONFIG_SPL_BUILD 151b20c38a9SStefan Roese #define CONFIG_SYS_MALLOC_SIMPLE 152b20c38a9SStefan Roese #endif 153b20c38a9SStefan Roese 154b20c38a9SStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 155b20c38a9SStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 156b20c38a9SStefan Roese 157b20c38a9SStefan Roese #define CONFIG_SPL_LIBCOMMON_SUPPORT 158b20c38a9SStefan Roese #define CONFIG_SPL_LIBGENERIC_SUPPORT 159b20c38a9SStefan Roese #define CONFIG_SPL_SERIAL_SUPPORT 160b20c38a9SStefan Roese #define CONFIG_SPL_I2C_SUPPORT 161b20c38a9SStefan Roese 162b20c38a9SStefan Roese /* SPL related SPI defines */ 163b20c38a9SStefan Roese #define CONFIG_SPL_SPI_SUPPORT 164b20c38a9SStefan Roese #define CONFIG_SPL_SPI_FLASH_SUPPORT 165b20c38a9SStefan Roese #define CONFIG_SPL_SPI_LOAD 166b20c38a9SStefan Roese #define CONFIG_SPL_SPI_BUS 0 167b20c38a9SStefan Roese #define CONFIG_SPL_SPI_CS 0 168b20c38a9SStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 169b20c38a9SStefan Roese #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 170b20c38a9SStefan Roese 171b20c38a9SStefan Roese /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 172b20c38a9SStefan Roese #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ 173b20c38a9SStefan Roese 174b20c38a9SStefan Roese #endif /* _CONFIG_THEADORABLE_H */ 175