1b20c38a9SStefan Roese /* 2b20c38a9SStefan Roese * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> 3b20c38a9SStefan Roese * 4b20c38a9SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5b20c38a9SStefan Roese */ 6b20c38a9SStefan Roese 7b20c38a9SStefan Roese #ifndef _CONFIG_THEADORABLE_H 8b20c38a9SStefan Roese #define _CONFIG_THEADORABLE_H 9b20c38a9SStefan Roese 10b20c38a9SStefan Roese /* 11b20c38a9SStefan Roese * High Level Configuration Options (easy to change) 12b20c38a9SStefan Roese */ 13b20c38a9SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 14b20c38a9SStefan Roese 15b20c38a9SStefan Roese /* 16b20c38a9SStefan Roese * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17b20c38a9SStefan Roese * for DDR ECC byte filling in the SPL before loading the main 18b20c38a9SStefan Roese * U-Boot into it. 19b20c38a9SStefan Roese */ 20b20c38a9SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00800000 21b20c38a9SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22b20c38a9SStefan Roese 23b20c38a9SStefan Roese /* 24b20c38a9SStefan Roese * Commands configuration 25b20c38a9SStefan Roese */ 26b20c38a9SStefan Roese 27b20c38a9SStefan Roese /* 28b20c38a9SStefan Roese * The debugging version enables USB support via defconfig. 29b20c38a9SStefan Roese * This version should also enable all other non-production 30b20c38a9SStefan Roese * interfaces / features. 31b20c38a9SStefan Roese */ 32b20c38a9SStefan Roese 33b20c38a9SStefan Roese /* I2C */ 34b20c38a9SStefan Roese #define CONFIG_SYS_I2C 35b20c38a9SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 36b20c38a9SStefan Roese #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 37*8ac71da9SStefan Roese #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE 38b20c38a9SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 39b20c38a9SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 40b20c38a9SStefan Roese 41b20c38a9SStefan Roese /* USB/EHCI configuration */ 42b20c38a9SStefan Roese #define CONFIG_EHCI_IS_TDI 43b20c38a9SStefan Roese #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 44b20c38a9SStefan Roese 45b20c38a9SStefan Roese /* SPI NOR flash default params, used by sf commands */ 46b20c38a9SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */ 47b20c38a9SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 48b20c38a9SStefan Roese 49b20c38a9SStefan Roese /* Environment in SPI NOR flash */ 50b20c38a9SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 51b20c38a9SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 52b20c38a9SStefan Roese #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 53b20c38a9SStefan Roese #define CONFIG_ENV_OVERWRITE 54b20c38a9SStefan Roese 55b20c38a9SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 56b20c38a9SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 57b20c38a9SStefan Roese 58b20c38a9SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 59b20c38a9SStefan Roese #define CONFIG_PREBOOT 60b20c38a9SStefan Roese 61b20c38a9SStefan Roese /* Keep device tree and initrd in lower memory so the kernel can access them */ 62b20c38a9SStefan Roese #define CONFIG_EXTRA_ENV_SETTINGS \ 63b20c38a9SStefan Roese "fdt_high=0x10000000\0" \ 64b20c38a9SStefan Roese "initrd_high=0x10000000\0" 65b20c38a9SStefan Roese 66b20c38a9SStefan Roese /* SATA support */ 67b20c38a9SStefan Roese #define CONFIG_SYS_SATA_MAX_DEVICE 1 68b20c38a9SStefan Roese #define CONFIG_SATA_MV 69b20c38a9SStefan Roese #define CONFIG_LIBATA 70b20c38a9SStefan Roese #define CONFIG_LBA48 71b20c38a9SStefan Roese 72b20c38a9SStefan Roese /* Additional FS support/configuration */ 73b20c38a9SStefan Roese #define CONFIG_SUPPORT_VFAT 74b20c38a9SStefan Roese 75b20c38a9SStefan Roese /* PCIe support */ 76b20c38a9SStefan Roese #ifdef CONFIG_CMD_PCI 77b20c38a9SStefan Roese #ifndef CONFIG_SPL_BUILD 78b20c38a9SStefan Roese #define CONFIG_PCI_MVEBU 79b20c38a9SStefan Roese #endif 80b20c38a9SStefan Roese #endif 81b20c38a9SStefan Roese 82b20c38a9SStefan Roese /* Enable LCD and reserve 512KB from top of memory*/ 83b20c38a9SStefan Roese #define CONFIG_SYS_MEM_TOP_HIDE 0x80000 84b20c38a9SStefan Roese 85aea02abeSStefan Roese /* FPGA programming support */ 86aea02abeSStefan Roese #define CONFIG_FPGA_STRATIX_V 87aea02abeSStefan Roese 88b20c38a9SStefan Roese /* 8928226b9aSStefan Roese * Bootcounter 9028226b9aSStefan Roese */ 9128226b9aSStefan Roese #define CONFIG_BOOTCOUNT_LIMIT 9228226b9aSStefan Roese #define CONFIG_BOOTCOUNT_RAM 9328226b9aSStefan Roese /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ 9428226b9aSStefan Roese #define BOOTCOUNT_ADDR 0x1000 9528226b9aSStefan Roese 9628226b9aSStefan Roese /* 97b20c38a9SStefan Roese * mv-common.h should be defined after CMD configs since it used them 98b20c38a9SStefan Roese * to enable certain macros 99b20c38a9SStefan Roese */ 100b20c38a9SStefan Roese #include "mv-common.h" 101b20c38a9SStefan Roese 102b20c38a9SStefan Roese /* 103b20c38a9SStefan Roese * Memory layout while starting into the bin_hdr via the 104b20c38a9SStefan Roese * BootROM: 105b20c38a9SStefan Roese * 106b20c38a9SStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 107b20c38a9SStefan Roese * 0x4000.4030 bin_hdr start address 108b20c38a9SStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 109b20c38a9SStefan Roese * 0x4007.fffc BootROM stack top 110b20c38a9SStefan Roese * 111b20c38a9SStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 112b20c38a9SStefan Roese * L2 cache thus cannot be used. 113b20c38a9SStefan Roese */ 114b20c38a9SStefan Roese 115b20c38a9SStefan Roese /* SPL */ 116b20c38a9SStefan Roese /* Defines for SPL */ 117b20c38a9SStefan Roese #define CONFIG_SPL_FRAMEWORK 118b20c38a9SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 119b20c38a9SStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 120b20c38a9SStefan Roese 121b20c38a9SStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 122b20c38a9SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 123b20c38a9SStefan Roese 124b20c38a9SStefan Roese #ifdef CONFIG_SPL_BUILD 125b20c38a9SStefan Roese #define CONFIG_SYS_MALLOC_SIMPLE 126b20c38a9SStefan Roese #endif 127b20c38a9SStefan Roese 128b20c38a9SStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 129b20c38a9SStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 130b20c38a9SStefan Roese 131b20c38a9SStefan Roese /* SPL related SPI defines */ 132b20c38a9SStefan Roese #define CONFIG_SPL_SPI_LOAD 133b20c38a9SStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 134b20c38a9SStefan Roese #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 135b20c38a9SStefan Roese 136b20c38a9SStefan Roese /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 137b20c38a9SStefan Roese #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ 138b20c38a9SStefan Roese 139b20c38a9SStefan Roese #endif /* _CONFIG_THEADORABLE_H */ 140