1f01b631fSTom Warren /* 2f01b631fSTom Warren * (C) Copyright 2010-2012 3f01b631fSTom Warren * NVIDIA Corporation <www.nvidia.com> 4f01b631fSTom Warren * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6f01b631fSTom Warren */ 7f01b631fSTom Warren 8f01b631fSTom Warren #ifndef _TEGRA30_COMMON_H_ 9f01b631fSTom Warren #define _TEGRA30_COMMON_H_ 10f01b631fSTom Warren #include "tegra-common.h" 11f01b631fSTom Warren 12f01b631fSTom Warren /* 13c44bb3a3SStephen Warren * Errata configuration 14c44bb3a3SStephen Warren */ 15c44bb3a3SStephen Warren #define CONFIG_ARM_ERRATA_743622 16c44bb3a3SStephen Warren #define CONFIG_ARM_ERRATA_751472 17c44bb3a3SStephen Warren 18c44bb3a3SStephen Warren /* 19f01b631fSTom Warren * NS16550 Configuration 20f01b631fSTom Warren */ 21f01b631fSTom Warren #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 22f01b631fSTom Warren 23f01b631fSTom Warren /* 24f01b631fSTom Warren * High Level Configuration Options 25f01b631fSTom Warren */ 26f01b631fSTom Warren #define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */ 27f01b631fSTom Warren 28f01b631fSTom Warren /* Environment information, boards can override if required */ 29f01b631fSTom Warren #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ 30f01b631fSTom Warren 31f01b631fSTom Warren /* 32f01b631fSTom Warren * Miscellaneous configurable options 33f01b631fSTom Warren */ 34f01b631fSTom Warren #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ 35f01b631fSTom Warren #define CONFIG_STACKBASE 0x82800000 /* 40MB */ 36f01b631fSTom Warren 37f01b631fSTom Warren /*----------------------------------------------------------------------- 38f01b631fSTom Warren * Physical Memory Map 39f01b631fSTom Warren */ 40f01b631fSTom Warren #define CONFIG_SYS_TEXT_BASE 0x8010E000 41f01b631fSTom Warren 42f01b631fSTom Warren /* 43f01b631fSTom Warren * Memory layout for where various images get loaded by boot scripts: 44f01b631fSTom Warren * 45f01b631fSTom Warren * scriptaddr can be pretty much anywhere that doesn't conflict with something 46f01b631fSTom Warren * else. Put it above BOOTMAPSZ to eliminate conflicts. 47f01b631fSTom Warren * 48f01b631fSTom Warren * kernel_addr_r must be within the first 128M of RAM in order for the 49f01b631fSTom Warren * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 50f01b631fSTom Warren * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 51f01b631fSTom Warren * should not overlap that area, or the kernel will have to copy itself 52f01b631fSTom Warren * somewhere else before decompression. Similarly, the address of any other 53f01b631fSTom Warren * data passed to the kernel shouldn't overlap the start of RAM. Pushing 54f01b631fSTom Warren * this up to 16M allows for a sizable kernel to be decompressed below the 55f01b631fSTom Warren * compressed load address. 56f01b631fSTom Warren * 57f01b631fSTom Warren * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 58f01b631fSTom Warren * the compressed kernel to be up to 16M too. 59f01b631fSTom Warren * 60f01b631fSTom Warren * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 61f01b631fSTom Warren * for the FDT/DTB to be up to 1M, which is hopefully plenty. 62f01b631fSTom Warren */ 63f01b631fSTom Warren #define MEM_LAYOUT_ENV_SETTINGS \ 64f01b631fSTom Warren "scriptaddr=0x90000000\0" \ 65f01b631fSTom Warren "kernel_addr_r=0x81000000\0" \ 66f01b631fSTom Warren "fdt_addr_r=0x82000000\0" \ 67f01b631fSTom Warren "ramdisk_addr_r=0x82100000\0" 68f01b631fSTom Warren 69f01b631fSTom Warren /* Defines for SPL */ 70f01b631fSTom Warren #define CONFIG_SPL_TEXT_BASE 0x80108000 71f01b631fSTom Warren #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 72f01b631fSTom Warren #define CONFIG_SPL_STACK 0x800ffffc 73f01b631fSTom Warren 74bb1e7cdeSTom Warren /* Total I2C ports on Tegra30 */ 75bb1e7cdeSTom Warren #define TEGRA_I2C_NUM_CONTROLLERS 5 76bb1e7cdeSTom Warren 77d6cf707eSJim Lin /* For USB EHCI controller */ 78d6cf707eSJim Lin #define CONFIG_EHCI_IS_TDI 79d6cf707eSJim Lin 80f01b631fSTom Warren #endif /* _TEGRA30_COMMON_H_ */ 81