1 /* 2 * (C) Copyright 2010-2012 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef __TEGRA20_COMMON_H 25 #define __TEGRA20_COMMON_H 26 #include <asm/sizes.h> 27 #include <linux/stringify.h> 28 29 /* 30 * High Level Configuration Options 31 */ 32 #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ 33 #define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ 34 #define CONFIG_TEGRA /* which is a Tegra generic machine */ 35 #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ 36 37 #define CONFIG_SYS_CACHELINE_SIZE 32 38 39 #include <asm/arch/tegra20.h> /* get chip and board defs */ 40 41 /* 42 * Display CPU and Board information 43 */ 44 #define CONFIG_DISPLAY_CPUINFO 45 #define CONFIG_DISPLAY_BOARDINFO 46 47 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 48 #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ 49 50 #ifdef CONFIG_TEGRA_LP0 51 #define TEGRA_LP0_ADDR 0x1C406000 52 #define TEGRA_LP0_SIZE 0x2000 53 #define TEGRA_LP0_VEC \ 54 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ 55 "@" __stringify(TEGRA_LP0_ADDR) " " 56 #else 57 #define TEGRA_LP0_VEC 58 #endif 59 60 /* Environment */ 61 #define CONFIG_ENV_VARS_UBOOT_CONFIG 62 #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ 63 64 /* 65 * Size of malloc() pool 66 */ 67 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ 68 69 /* 70 * PllX Configuration 71 */ 72 #define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */ 73 74 /* 75 * NS16550 Configuration 76 */ 77 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ 78 79 #define CONFIG_SYS_NS16550 80 #define CONFIG_SYS_NS16550_SERIAL 81 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 82 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 83 84 /* 85 * select serial console configuration 86 */ 87 #define CONFIG_CONS_INDEX 1 88 89 /* allow to overwrite serial and ethaddr */ 90 #define CONFIG_ENV_OVERWRITE 91 #define CONFIG_BAUDRATE 115200 92 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 93 115200} 94 95 /* 96 * This parameter affects a TXFILLTUNING field that controls how much data is 97 * sent to the latency fifo before it is sent to the wire. Without this 98 * parameter, the default (2) causes occasional Data Buffer Errors in OUT 99 * packets depending on the buffer address and size. 100 */ 101 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 102 #define CONFIG_EHCI_IS_TDI 103 #define CONFIG_EHCI_DCACHE 104 105 /* Total I2C ports on Tegra20 */ 106 #define TEGRA_I2C_NUM_CONTROLLERS 4 107 108 /* include default commands */ 109 #include <config_cmd_default.h> 110 111 /* remove unused commands */ 112 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 113 #undef CONFIG_CMD_FPGA /* FPGA configuration support */ 114 #undef CONFIG_CMD_IMI 115 #undef CONFIG_CMD_IMLS 116 #undef CONFIG_CMD_NFS /* NFS support */ 117 #undef CONFIG_CMD_NET /* network support */ 118 119 /* turn on command-line edit/hist/auto */ 120 #define CONFIG_CMDLINE_EDITING 121 #define CONFIG_COMMAND_HISTORY 122 #define CONFIG_AUTO_COMPLETE 123 124 #define CONFIG_SYS_NO_FLASH 125 126 /* Environment information, boards can override if required */ 127 #define CONFIG_CONSOLE_MUX 128 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 129 #define TEGRA_DEVICE_SETTINGS "stdin=serial\0" \ 130 "stdout=serial\0" \ 131 "stderr=serial\0" 132 133 #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ 134 #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ 135 136 /* 137 * Miscellaneous configurable options 138 */ 139 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 140 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 141 #define CONFIG_SYS_PROMPT V_PROMPT 142 /* 143 * Increasing the size of the IO buffer as default nfsargs size is more 144 * than 256 and so it is not possible to edit it 145 */ 146 #define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ 147 /* Print Buffer Size */ 148 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 149 sizeof(CONFIG_SYS_PROMPT) + 16) 150 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 151 /* Boot Argument Buffer Size */ 152 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 153 154 #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) 155 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) 156 157 #define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */ 158 #define CONFIG_SYS_HZ 1000 159 160 #define CONFIG_STACKBASE 0x2800000 /* 40MB */ 161 162 /*----------------------------------------------------------------------- 163 * Physical Memory Map 164 */ 165 #define CONFIG_NR_DRAM_BANKS 1 166 #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 167 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ 168 169 #define CONFIG_SYS_TEXT_BASE 0x0010c000 170 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 171 172 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE 173 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN 174 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 175 CONFIG_SYS_INIT_RAM_SIZE - \ 176 GENERATED_GBL_DATA_SIZE) 177 178 #define CONFIG_TEGRA_GPIO 179 #define CONFIG_CMD_GPIO 180 #define CONFIG_CMD_ENTERRCM 181 #define CONFIG_CMD_BOOTZ 182 183 /* Defines for SPL */ 184 #define CONFIG_SPL 185 #define CONFIG_SPL_NAND_SIMPLE 186 #define CONFIG_SPL_TEXT_BASE 0x00108000 187 #define CONFIG_SPL_MAX_SIZE 0x00004000 188 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 189 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 190 #define CONFIG_SPL_STACK 0x000ffffc 191 192 #define CONFIG_SPL_LIBCOMMON_SUPPORT 193 #define CONFIG_SPL_LIBGENERIC_SUPPORT 194 #define CONFIG_SPL_SERIAL_SUPPORT 195 #define CONFIG_SPL_GPIO_SUPPORT 196 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds" 197 198 #define CONFIG_SYS_NAND_SELF_INIT 199 200 #endif /* __TEGRA20_COMMON_H */ 201