1*c7ba99c8SStephen Warren /* 2*c7ba99c8SStephen Warren * Copyright 2013-2016, NVIDIA CORPORATION. 3*c7ba99c8SStephen Warren * 4*c7ba99c8SStephen Warren * SPDX-License-Identifier: GPL-2.0 5*c7ba99c8SStephen Warren */ 6*c7ba99c8SStephen Warren 7*c7ba99c8SStephen Warren #ifndef _TEGRA186_COMMON_H_ 8*c7ba99c8SStephen Warren #define _TEGRA186_COMMON_H_ 9*c7ba99c8SStephen Warren 10*c7ba99c8SStephen Warren #include "tegra-common.h" 11*c7ba99c8SStephen Warren 12*c7ba99c8SStephen Warren /* Cortex-A57 uses a cache line size of 64 bytes */ 13*c7ba99c8SStephen Warren #define CONFIG_SYS_CACHELINE_SIZE 64 14*c7ba99c8SStephen Warren 15*c7ba99c8SStephen Warren /* 16*c7ba99c8SStephen Warren * NS16550 Configuration 17*c7ba99c8SStephen Warren */ 18*c7ba99c8SStephen Warren #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 19*c7ba99c8SStephen Warren 20*c7ba99c8SStephen Warren /* 21*c7ba99c8SStephen Warren * Miscellaneous configurable options 22*c7ba99c8SStephen Warren */ 23*c7ba99c8SStephen Warren #define CONFIG_STACKBASE 0x82800000 /* 40MB */ 24*c7ba99c8SStephen Warren 25*c7ba99c8SStephen Warren /*----------------------------------------------------------------------- 26*c7ba99c8SStephen Warren * Physical Memory Map 27*c7ba99c8SStephen Warren */ 28*c7ba99c8SStephen Warren 29*c7ba99c8SStephen Warren #define CONFIG_SYS_TEXT_BASE 0x80080000 30*c7ba99c8SStephen Warren 31*c7ba99c8SStephen Warren /* Generic Interrupt Controller */ 32*c7ba99c8SStephen Warren #define CONFIG_GICV2 33*c7ba99c8SStephen Warren 34*c7ba99c8SStephen Warren /* 35*c7ba99c8SStephen Warren * Memory layout for where various images get loaded by boot scripts: 36*c7ba99c8SStephen Warren * 37*c7ba99c8SStephen Warren * scriptaddr can be pretty much anywhere that doesn't conflict with something 38*c7ba99c8SStephen Warren * else. Put it above BOOTMAPSZ to eliminate conflicts. 39*c7ba99c8SStephen Warren * 40*c7ba99c8SStephen Warren * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 41*c7ba99c8SStephen Warren * something else. Put it above BOOTMAPSZ to eliminate conflicts. 42*c7ba99c8SStephen Warren * 43*c7ba99c8SStephen Warren * kernel_addr_r must be within the first 128M of RAM in order for the 44*c7ba99c8SStephen Warren * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 45*c7ba99c8SStephen Warren * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 46*c7ba99c8SStephen Warren * should not overlap that area, or the kernel will have to copy itself 47*c7ba99c8SStephen Warren * somewhere else before decompression. Similarly, the address of any other 48*c7ba99c8SStephen Warren * data passed to the kernel shouldn't overlap the start of RAM. Pushing 49*c7ba99c8SStephen Warren * this up to 16M allows for a sizable kernel to be decompressed below the 50*c7ba99c8SStephen Warren * compressed load address. 51*c7ba99c8SStephen Warren * 52*c7ba99c8SStephen Warren * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 53*c7ba99c8SStephen Warren * the compressed kernel to be up to 16M too. 54*c7ba99c8SStephen Warren * 55*c7ba99c8SStephen Warren * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 56*c7ba99c8SStephen Warren * for the FDT/DTB to be up to 1M, which is hopefully plenty. 57*c7ba99c8SStephen Warren */ 58*c7ba99c8SStephen Warren #define CONFIG_LOADADDR 0x80080000 59*c7ba99c8SStephen Warren #define MEM_LAYOUT_ENV_SETTINGS \ 60*c7ba99c8SStephen Warren "scriptaddr=0x90000000\0" \ 61*c7ba99c8SStephen Warren "pxefile_addr_r=0x90100000\0" \ 62*c7ba99c8SStephen Warren "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 63*c7ba99c8SStephen Warren "fdt_addr_r=0x82000000\0" \ 64*c7ba99c8SStephen Warren "ramdisk_addr_r=0x82100000\0" 65*c7ba99c8SStephen Warren 66*c7ba99c8SStephen Warren /* Defines for SPL */ 67*c7ba99c8SStephen Warren #define CONFIG_SPL_TEXT_BASE 0x80108000 68*c7ba99c8SStephen Warren #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 69*c7ba99c8SStephen Warren #define CONFIG_SPL_STACK 0x800ffffc 70*c7ba99c8SStephen Warren 71*c7ba99c8SStephen Warren #endif 72