1*f7dc4ac3STom Warren /* 2*f7dc4ac3STom Warren * (C) Copyright 2013 3*f7dc4ac3STom Warren * NVIDIA Corporation <www.nvidia.com> 4*f7dc4ac3STom Warren * 5*f7dc4ac3STom Warren * SPDX-License-Identifier: GPL-2.0+ 6*f7dc4ac3STom Warren */ 7*f7dc4ac3STom Warren 8*f7dc4ac3STom Warren #ifndef _TEGRA124_COMMON_H_ 9*f7dc4ac3STom Warren #define _TEGRA124_COMMON_H_ 10*f7dc4ac3STom Warren 11*f7dc4ac3STom Warren #include "tegra-common.h" 12*f7dc4ac3STom Warren 13*f7dc4ac3STom Warren /* Cortex-A15 uses a cache line size of 64 bytes */ 14*f7dc4ac3STom Warren #define CONFIG_SYS_CACHELINE_SIZE 64 15*f7dc4ac3STom Warren 16*f7dc4ac3STom Warren /* 17*f7dc4ac3STom Warren * NS16550 Configuration 18*f7dc4ac3STom Warren */ 19*f7dc4ac3STom Warren #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 20*f7dc4ac3STom Warren 21*f7dc4ac3STom Warren /* 22*f7dc4ac3STom Warren * High Level Configuration Options 23*f7dc4ac3STom Warren */ 24*f7dc4ac3STom Warren #define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */ 25*f7dc4ac3STom Warren 26*f7dc4ac3STom Warren /* Environment information, boards can override if required */ 27*f7dc4ac3STom Warren #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ 28*f7dc4ac3STom Warren 29*f7dc4ac3STom Warren /* 30*f7dc4ac3STom Warren * Miscellaneous configurable options 31*f7dc4ac3STom Warren */ 32*f7dc4ac3STom Warren #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ 33*f7dc4ac3STom Warren #define CONFIG_STACKBASE 0x82800000 /* 40MB */ 34*f7dc4ac3STom Warren 35*f7dc4ac3STom Warren /*----------------------------------------------------------------------- 36*f7dc4ac3STom Warren * Physical Memory Map 37*f7dc4ac3STom Warren */ 38*f7dc4ac3STom Warren #define CONFIG_SYS_TEXT_BASE 0x8010E000 39*f7dc4ac3STom Warren 40*f7dc4ac3STom Warren /* 41*f7dc4ac3STom Warren * Memory layout for where various images get loaded by boot scripts: 42*f7dc4ac3STom Warren * 43*f7dc4ac3STom Warren * scriptaddr can be pretty much anywhere that doesn't conflict with something 44*f7dc4ac3STom Warren * else. Put it above BOOTMAPSZ to eliminate conflicts. 45*f7dc4ac3STom Warren * 46*f7dc4ac3STom Warren * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 47*f7dc4ac3STom Warren * something else. Put it above BOOTMAPSZ to eliminate conflicts. 48*f7dc4ac3STom Warren * 49*f7dc4ac3STom Warren * kernel_addr_r must be within the first 128M of RAM in order for the 50*f7dc4ac3STom Warren * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 51*f7dc4ac3STom Warren * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 52*f7dc4ac3STom Warren * should not overlap that area, or the kernel will have to copy itself 53*f7dc4ac3STom Warren * somewhere else before decompression. Similarly, the address of any other 54*f7dc4ac3STom Warren * data passed to the kernel shouldn't overlap the start of RAM. Pushing 55*f7dc4ac3STom Warren * this up to 16M allows for a sizable kernel to be decompressed below the 56*f7dc4ac3STom Warren * compressed load address. 57*f7dc4ac3STom Warren * 58*f7dc4ac3STom Warren * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 59*f7dc4ac3STom Warren * the compressed kernel to be up to 16M too. 60*f7dc4ac3STom Warren * 61*f7dc4ac3STom Warren * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 62*f7dc4ac3STom Warren * for the FDT/DTB to be up to 1M, which is hopefully plenty. 63*f7dc4ac3STom Warren */ 64*f7dc4ac3STom Warren #define MEM_LAYOUT_ENV_SETTINGS \ 65*f7dc4ac3STom Warren "scriptaddr=0x90000000\0" \ 66*f7dc4ac3STom Warren "pxefile_addr_r=0x90100000\0" \ 67*f7dc4ac3STom Warren "kernel_addr_r=0x81000000\0" \ 68*f7dc4ac3STom Warren "fdt_addr_r=0x82000000\0" \ 69*f7dc4ac3STom Warren "ramdisk_addr_r=0x82100000\0" 70*f7dc4ac3STom Warren 71*f7dc4ac3STom Warren /* Defines for SPL */ 72*f7dc4ac3STom Warren #define CONFIG_SPL_TEXT_BASE 0x80108000 73*f7dc4ac3STom Warren #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 74*f7dc4ac3STom Warren #define CONFIG_SPL_STACK 0x800ffffc 75*f7dc4ac3STom Warren 76*f7dc4ac3STom Warren /* Total I2C ports on Tegra124 */ 77*f7dc4ac3STom Warren #define TEGRA_I2C_NUM_CONTROLLERS 5 78*f7dc4ac3STom Warren 79*f7dc4ac3STom Warren /* For USB EHCI controller */ 80*f7dc4ac3STom Warren #define CONFIG_EHCI_IS_TDI 81*f7dc4ac3STom Warren 82*f7dc4ac3STom Warren #endif /* _TEGRA124_COMMON_H_ */ 83