1f7dc4ac3STom Warren /* 2f7dc4ac3STom Warren * (C) Copyright 2013 3f7dc4ac3STom Warren * NVIDIA Corporation <www.nvidia.com> 4f7dc4ac3STom Warren * 5f7dc4ac3STom Warren * SPDX-License-Identifier: GPL-2.0+ 6f7dc4ac3STom Warren */ 7f7dc4ac3STom Warren 8f7dc4ac3STom Warren #ifndef _TEGRA124_COMMON_H_ 9f7dc4ac3STom Warren #define _TEGRA124_COMMON_H_ 10f7dc4ac3STom Warren 11f7dc4ac3STom Warren #include "tegra-common.h" 12f7dc4ac3STom Warren 13f7dc4ac3STom Warren /* Cortex-A15 uses a cache line size of 64 bytes */ 14f7dc4ac3STom Warren #define CONFIG_SYS_CACHELINE_SIZE 64 15f7dc4ac3STom Warren 16f7dc4ac3STom Warren /* 17f7dc4ac3STom Warren * NS16550 Configuration 18f7dc4ac3STom Warren */ 19f7dc4ac3STom Warren #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 20f7dc4ac3STom Warren 21f7dc4ac3STom Warren /* 22f7dc4ac3STom Warren * Miscellaneous configurable options 23f7dc4ac3STom Warren */ 24f7dc4ac3STom Warren #define CONFIG_STACKBASE 0x82800000 /* 40MB */ 25f7dc4ac3STom Warren 26f7dc4ac3STom Warren /*----------------------------------------------------------------------- 27f7dc4ac3STom Warren * Physical Memory Map 28f7dc4ac3STom Warren */ 29f7dc4ac3STom Warren #define CONFIG_SYS_TEXT_BASE 0x8010E000 30f7dc4ac3STom Warren 31f7dc4ac3STom Warren /* 32f7dc4ac3STom Warren * Memory layout for where various images get loaded by boot scripts: 33f7dc4ac3STom Warren * 34f7dc4ac3STom Warren * scriptaddr can be pretty much anywhere that doesn't conflict with something 35f7dc4ac3STom Warren * else. Put it above BOOTMAPSZ to eliminate conflicts. 36f7dc4ac3STom Warren * 37f7dc4ac3STom Warren * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 38f7dc4ac3STom Warren * something else. Put it above BOOTMAPSZ to eliminate conflicts. 39f7dc4ac3STom Warren * 40f7dc4ac3STom Warren * kernel_addr_r must be within the first 128M of RAM in order for the 41f7dc4ac3STom Warren * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 42f7dc4ac3STom Warren * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 43f7dc4ac3STom Warren * should not overlap that area, or the kernel will have to copy itself 44f7dc4ac3STom Warren * somewhere else before decompression. Similarly, the address of any other 45f7dc4ac3STom Warren * data passed to the kernel shouldn't overlap the start of RAM. Pushing 46f7dc4ac3STom Warren * this up to 16M allows for a sizable kernel to be decompressed below the 47f7dc4ac3STom Warren * compressed load address. 48f7dc4ac3STom Warren * 49f7dc4ac3STom Warren * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 50f7dc4ac3STom Warren * the compressed kernel to be up to 16M too. 51f7dc4ac3STom Warren * 52f7dc4ac3STom Warren * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 53f7dc4ac3STom Warren * for the FDT/DTB to be up to 1M, which is hopefully plenty. 54f7dc4ac3STom Warren */ 55*48cfca24SStephen Warren #define CONFIG_LOADADDR 0x81000000 56f7dc4ac3STom Warren #define MEM_LAYOUT_ENV_SETTINGS \ 57f7dc4ac3STom Warren "scriptaddr=0x90000000\0" \ 58f7dc4ac3STom Warren "pxefile_addr_r=0x90100000\0" \ 59*48cfca24SStephen Warren "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 60f7dc4ac3STom Warren "fdt_addr_r=0x82000000\0" \ 61f7dc4ac3STom Warren "ramdisk_addr_r=0x82100000\0" 62f7dc4ac3STom Warren 63f7dc4ac3STom Warren /* Defines for SPL */ 64f7dc4ac3STom Warren #define CONFIG_SPL_TEXT_BASE 0x80108000 65f7dc4ac3STom Warren #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 66f7dc4ac3STom Warren #define CONFIG_SPL_STACK 0x800ffffc 67f7dc4ac3STom Warren 68f7dc4ac3STom Warren /* For USB EHCI controller */ 69f7dc4ac3STom Warren #define CONFIG_EHCI_IS_TDI 707bc5c8c9SJim Lin #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 71f75dc784SStephen Warren #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 72f7dc4ac3STom Warren 73f7dc4ac3STom Warren #endif /* _TEGRA124_COMMON_H_ */ 74