107067145STom Warren /* 207067145STom Warren * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 307067145STom Warren * 4*5b8031ccSTom Rini * SPDX-License-Identifier: GPL-2.0 507067145STom Warren */ 607067145STom Warren 707067145STom Warren #ifndef _TEGRA114_COMMON_H_ 807067145STom Warren #define _TEGRA114_COMMON_H_ 907067145STom Warren #include "tegra-common.h" 1007067145STom Warren 110d79f4f4SThierry Reding /* Cortex-A15 uses a cache line size of 64 bytes */ 120d79f4f4SThierry Reding #define CONFIG_SYS_CACHELINE_SIZE 64 130d79f4f4SThierry Reding 1407067145STom Warren /* 1507067145STom Warren * NS16550 Configuration 1607067145STom Warren */ 1707067145STom Warren #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ 1807067145STom Warren 1907067145STom Warren /* 2007067145STom Warren * Miscellaneous configurable options 2107067145STom Warren */ 2207067145STom Warren #define CONFIG_STACKBASE 0x82800000 /* 40MB */ 2307067145STom Warren 2407067145STom Warren /*----------------------------------------------------------------------- 2507067145STom Warren * Physical Memory Map 2607067145STom Warren */ 27930c514dSStephen Warren #define CONFIG_SYS_TEXT_BASE 0x80110000 2807067145STom Warren 2907067145STom Warren /* 3007067145STom Warren * Memory layout for where various images get loaded by boot scripts: 3107067145STom Warren * 3207067145STom Warren * scriptaddr can be pretty much anywhere that doesn't conflict with something 3307067145STom Warren * else. Put it above BOOTMAPSZ to eliminate conflicts. 3407067145STom Warren * 35f940c72eSStephen Warren * pxefile_addr_r can be pretty much anywhere that doesn't conflict with 36f940c72eSStephen Warren * something else. Put it above BOOTMAPSZ to eliminate conflicts. 37f940c72eSStephen Warren * 3807067145STom Warren * kernel_addr_r must be within the first 128M of RAM in order for the 3907067145STom Warren * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will 4007067145STom Warren * decompress itself to 0x8000 after the start of RAM, kernel_addr_r 4107067145STom Warren * should not overlap that area, or the kernel will have to copy itself 4207067145STom Warren * somewhere else before decompression. Similarly, the address of any other 4307067145STom Warren * data passed to the kernel shouldn't overlap the start of RAM. Pushing 4407067145STom Warren * this up to 16M allows for a sizable kernel to be decompressed below the 4507067145STom Warren * compressed load address. 4607067145STom Warren * 4707067145STom Warren * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for 4807067145STom Warren * the compressed kernel to be up to 16M too. 4907067145STom Warren * 5007067145STom Warren * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows 5107067145STom Warren * for the FDT/DTB to be up to 1M, which is hopefully plenty. 5207067145STom Warren */ 5348cfca24SStephen Warren #define CONFIG_LOADADDR 0x81000000 5407067145STom Warren #define MEM_LAYOUT_ENV_SETTINGS \ 5507067145STom Warren "scriptaddr=0x90000000\0" \ 56f940c72eSStephen Warren "pxefile_addr_r=0x90100000\0" \ 5748cfca24SStephen Warren "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ 5807067145STom Warren "fdt_addr_r=0x82000000\0" \ 5907067145STom Warren "ramdisk_addr_r=0x82100000\0" 6007067145STom Warren 6107067145STom Warren /* Defines for SPL */ 6207067145STom Warren #define CONFIG_SPL_TEXT_BASE 0x80108000 6307067145STom Warren #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 6407067145STom Warren #define CONFIG_SPL_STACK 0x800ffffc 6507067145STom Warren 66d6cf707eSJim Lin /* For USB EHCI controller */ 67d6cf707eSJim Lin #define CONFIG_EHCI_IS_TDI 6881d21e98SJim Lin #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 69f75dc784SStephen Warren #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 70d6cf707eSJim Lin 7107067145STom Warren #endif /* _TEGRA114_COMMON_H_ */ 72