xref: /rk3399_rockchip-uboot/include/configs/tbs2910.h (revision c6745195be700fa3f8a7221169a0f20df9c0e91f)
1 /*
2  * Copyright (C) 2014 Soeren Moch <smoch@web.de>
3  *
4  * Configuration settings for the TBS2910 MatrixARM board.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __TBS2910_CONFIG_H
10 #define __TBS2910_CONFIG_H
11 
12 #include "mx6_common.h"
13 
14 /* General configuration */
15 #define CONFIG_SYS_THUMB_BUILD
16 
17 #define CONFIG_MACH_TYPE		3980
18 
19 #define CONFIG_BOARD_EARLY_INIT_F
20 
21 #define CONFIG_SYS_HZ			1000
22 
23 #define CONFIG_IMX_THERMAL
24 
25 /* Physical Memory Map */
26 #define CONFIG_NR_DRAM_BANKS		1
27 #define CONFIG_SYS_SDRAM_BASE		MMDC0_ARB_BASE_ADDR
28 
29 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
30 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
31 #define CONFIG_SYS_INIT_SP_OFFSET \
32 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
33 #define CONFIG_SYS_INIT_SP_ADDR \
34 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
35 
36 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024 * 1024)
37 
38 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
39 #define CONFIG_SYS_MEMTEST_END \
40 	(CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
41 
42 #define CONFIG_SYS_BOOTMAPSZ		0x10000000
43 
44 /* Serial console */
45 #define CONFIG_MXC_UART
46 #define CONFIG_MXC_UART_BASE		UART1_BASE /* select UART1/UART2 */
47 #define CONFIG_BAUDRATE			115200
48 
49 #define CONFIG_CONS_INDEX		1
50 
51 /* *** Command definition *** */
52 #define CONFIG_CMD_BMODE
53 #define CONFIG_CMD_PART
54 
55 /* Filesystems / image support */
56 #define CONFIG_EFI_PARTITION
57 #define CONFIG_PARTITION_UUIDS
58 
59 /* MMC */
60 #define CONFIG_SYS_FSL_USDHC_NUM	3
61 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
62 #define CONFIG_SUPPORT_EMMC_BOOT
63 
64 /* Ethernet */
65 #define CONFIG_FEC_MXC
66 #define CONFIG_FEC_MXC
67 #define CONFIG_MII
68 #define IMX_FEC_BASE			ENET_BASE_ADDR
69 #define CONFIG_FEC_XCV_TYPE		RGMII
70 #define CONFIG_ETHPRIME			"FEC"
71 #define CONFIG_FEC_MXC_PHYADDR		4
72 #define CONFIG_PHYLIB
73 #define CONFIG_PHY_ATHEROS
74 
75 /* Framebuffer */
76 #ifdef CONFIG_VIDEO
77 #define CONFIG_VIDEO_IPUV3
78 #define CONFIG_IPUV3_CLK		260000000
79 #define CONFIG_VIDEO_SW_CURSOR
80 #define CONFIG_VGA_AS_SINGLE_DEVICE
81 #define CONFIG_VIDEO_BMP_RLE8
82 #define CONFIG_IMX_HDMI
83 #define CONFIG_IMX_VIDEO_SKIP
84 #define CONFIG_CMD_HDMIDETECT
85 #endif
86 
87 /* PCI */
88 #define CONFIG_CMD_PCI
89 #ifdef CONFIG_CMD_PCI
90 #define CONFIG_PCI
91 #define CONFIG_PCI_PNP
92 #define CONFIG_PCI_SCAN_SHOW
93 #define CONFIG_PCIE_IMX
94 #define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
95 #endif
96 
97 /* SATA */
98 #define CONFIG_CMD_SATA
99 #ifdef CONFIG_CMD_SATA
100 #define CONFIG_DWC_AHSATA
101 #define CONFIG_SYS_SATA_MAX_DEVICE	1
102 #define CONFIG_DWC_AHSATA_PORT_ID	0
103 #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
104 #define CONFIG_LBA48
105 #define CONFIG_LIBATA
106 #endif
107 
108 /* USB */
109 #ifdef CONFIG_CMD_USB
110 #define CONFIG_USB_EHCI
111 #define CONFIG_USB_EHCI_MX6
112 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
113 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
114 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
115 #ifdef CONFIG_CMD_USB_MASS_STORAGE
116 #define CONFIG_USBD_HS
117 #define CONFIG_USB_FUNCTION_MASS_STORAGE
118 #endif /* CONFIG_CMD_USB_MASS_STORAGE */
119 #define CONFIG_USB_KEYBOARD
120 #ifdef CONFIG_USB_KEYBOARD
121 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
122 #define CONFIG_SYS_STDIO_DEREGISTER
123 #define CONFIG_PREBOOT \
124 	"usb start; " \
125 	"if hdmidet; then " \
126 		"run set_con_hdmi; " \
127 	"else " \
128 		"run set_con_serial; " \
129 	"fi;"
130 #endif /* CONFIG_USB_KEYBOARD */
131 #endif /* CONFIG_CMD_USB      */
132 
133 /* RTC */
134 #define CONFIG_CMD_DATE
135 #ifdef CONFIG_CMD_DATE
136 #define CONFIG_RTC_DS1307
137 #define CONFIG_SYS_RTC_BUS_NUM		2
138 #endif
139 
140 /* I2C */
141 #ifdef CONFIG_CMD_I2C
142 #define CONFIG_SYS_I2C
143 #define CONFIG_SYS_I2C_MXC
144 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
145 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
146 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
147 #define CONFIG_SYS_I2C_SPEED		100000
148 #define CONFIG_I2C_EDID
149 #endif
150 
151 /* Environment organization */
152 #define CONFIG_ENV_IS_IN_MMC
153 #define CONFIG_SYS_MMC_ENV_DEV		2 /* overwritten on SD boot */
154 #define CONFIG_SYS_MMC_ENV_PART		1 /* overwritten on SD boot */
155 #define CONFIG_ENV_SIZE			(8 * 1024)
156 #define CONFIG_ENV_OFFSET		(384 * 1024)
157 #define CONFIG_ENV_OVERWRITE
158 
159 #define CONFIG_EXTRA_ENV_SETTINGS \
160 	"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
161 	"bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
162 			"video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
163 	"bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
164 	"bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
165 			"${bootargs_mmc3}\0" \
166 	"bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
167 			"rdinit=/sbin/init enable_wait_mode=off\0" \
168 	"bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
169 			"mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
170 	"bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
171 	"bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
172 			"run bootargs_upd; " \
173 			"bootm 0x10800000 0x10d00000\0" \
174 	"console=ttymxc0\0" \
175 	"fan=gpio set 92\0" \
176 	"set_con_serial=setenv stdout serial; " \
177 			"setenv stderr serial;\0" \
178 	"set_con_hdmi=setenv stdout serial,vga; " \
179 			"setenv stderr serial,vga;\0" \
180 	"stderr=serial,vga;\0" \
181 	"stdin=serial,usbkbd;\0" \
182 	"stdout=serial,vga;\0"
183 
184 #define CONFIG_BOOTCOMMAND \
185 	"mmc rescan; " \
186 	"if run bootcmd_up1; then " \
187 		"run bootcmd_up2; " \
188 	"else " \
189 		"run bootcmd_mmc; " \
190 	"fi"
191 
192 #endif			       /* __TBS2910_CONFIG_H * */
193