xref: /rk3399_rockchip-uboot/include/configs/tbs2910.h (revision 4ef6ecec9cdf1ce4c7b4f2a6b0f903583bfa24a2)
1 /*
2  * Copyright (C) 2014 Soeren Moch <smoch@web.de>
3  *
4  * Configuration settings for the TBS2910 MatrixARM board.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __TBS2910_CONFIG_H
10 #define __TBS2910_CONFIG_H
11 
12 #include "mx6_common.h"
13 
14 /* General configuration */
15 #define CONFIG_SYS_THUMB_BUILD
16 
17 #define CONFIG_MACH_TYPE		3980
18 
19 #define CONFIG_BOARD_EARLY_INIT_F
20 
21 #define CONFIG_SYS_HZ			1000
22 
23 #define CONFIG_IMX_THERMAL
24 
25 /* Physical Memory Map */
26 #define CONFIG_NR_DRAM_BANKS		1
27 #define CONFIG_SYS_SDRAM_BASE		MMDC0_ARB_BASE_ADDR
28 
29 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
30 #define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
31 #define CONFIG_SYS_INIT_SP_OFFSET \
32 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
33 #define CONFIG_SYS_INIT_SP_ADDR \
34 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
35 
36 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024 * 1024)
37 
38 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
39 #define CONFIG_SYS_MEMTEST_END \
40 	(CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
41 
42 #define CONFIG_SYS_BOOTMAPSZ		0x10000000
43 
44 /* Serial console */
45 #define CONFIG_MXC_UART
46 #define CONFIG_MXC_UART_BASE		UART1_BASE /* select UART1/UART2 */
47 #define CONFIG_BAUDRATE			115200
48 
49 #define CONFIG_CONS_INDEX		1
50 
51 /* *** Command definition *** */
52 #define CONFIG_CMD_BMODE
53 #define CONFIG_CMD_PART
54 
55 /* Filesystems / image support */
56 #define CONFIG_EFI_PARTITION
57 #define CONFIG_PARTITION_UUIDS
58 
59 /* MMC */
60 #define CONFIG_SYS_FSL_USDHC_NUM	3
61 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
62 #define CONFIG_SUPPORT_EMMC_BOOT
63 
64 /* Ethernet */
65 #define CONFIG_FEC_MXC
66 #define CONFIG_FEC_MXC
67 #define CONFIG_MII
68 #define IMX_FEC_BASE			ENET_BASE_ADDR
69 #define CONFIG_FEC_XCV_TYPE		RGMII
70 #define CONFIG_ETHPRIME			"FEC"
71 #define CONFIG_FEC_MXC_PHYADDR		4
72 #define CONFIG_PHYLIB
73 #define CONFIG_PHY_ATHEROS
74 
75 /* Framebuffer */
76 #ifdef CONFIG_VIDEO
77 #define CONFIG_VIDEO_IPUV3
78 #define CONFIG_IPUV3_CLK		260000000
79 #define CONFIG_VIDEO_BMP_RLE8
80 #define CONFIG_IMX_HDMI
81 #define CONFIG_IMX_VIDEO_SKIP
82 #define CONFIG_CMD_HDMIDETECT
83 #endif
84 
85 /* PCI */
86 #define CONFIG_CMD_PCI
87 #ifdef CONFIG_CMD_PCI
88 #define CONFIG_PCI
89 #define CONFIG_PCI_PNP
90 #define CONFIG_PCI_SCAN_SHOW
91 #define CONFIG_PCIE_IMX
92 #define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
93 #endif
94 
95 /* SATA */
96 #define CONFIG_CMD_SATA
97 #ifdef CONFIG_CMD_SATA
98 #define CONFIG_DWC_AHSATA
99 #define CONFIG_SYS_SATA_MAX_DEVICE	1
100 #define CONFIG_DWC_AHSATA_PORT_ID	0
101 #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
102 #define CONFIG_LBA48
103 #define CONFIG_LIBATA
104 #endif
105 
106 /* USB */
107 #ifdef CONFIG_CMD_USB
108 #define CONFIG_USB_EHCI
109 #define CONFIG_USB_EHCI_MX6
110 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
111 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
112 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
113 #ifdef CONFIG_CMD_USB_MASS_STORAGE
114 #define CONFIG_USBD_HS
115 #define CONFIG_USB_FUNCTION_MASS_STORAGE
116 #endif /* CONFIG_CMD_USB_MASS_STORAGE */
117 #ifdef CONFIG_USB_KEYBOARD
118 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
119 #define CONFIG_SYS_STDIO_DEREGISTER
120 #define CONFIG_PREBOOT \
121 	"usb start; " \
122 	"if hdmidet; then " \
123 		"run set_con_hdmi; " \
124 	"else " \
125 		"run set_con_serial; " \
126 	"fi;"
127 #endif /* CONFIG_USB_KEYBOARD */
128 #endif /* CONFIG_CMD_USB      */
129 
130 /* RTC */
131 #define CONFIG_CMD_DATE
132 #ifdef CONFIG_CMD_DATE
133 #define CONFIG_RTC_DS1307
134 #define CONFIG_SYS_RTC_BUS_NUM		2
135 #endif
136 
137 /* I2C */
138 #ifdef CONFIG_CMD_I2C
139 #define CONFIG_SYS_I2C
140 #define CONFIG_SYS_I2C_MXC
141 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
142 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
143 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
144 #define CONFIG_SYS_I2C_SPEED		100000
145 #define CONFIG_I2C_EDID
146 #endif
147 
148 /* Environment organization */
149 #define CONFIG_ENV_IS_IN_MMC
150 #define CONFIG_SYS_MMC_ENV_DEV		2 /* overwritten on SD boot */
151 #define CONFIG_SYS_MMC_ENV_PART		1 /* overwritten on SD boot */
152 #define CONFIG_ENV_SIZE			(8 * 1024)
153 #define CONFIG_ENV_OFFSET		(384 * 1024)
154 #define CONFIG_ENV_OVERWRITE
155 
156 #define CONFIG_EXTRA_ENV_SETTINGS \
157 	"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
158 	"bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
159 			"video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
160 	"bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
161 	"bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
162 			"${bootargs_mmc3}\0" \
163 	"bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
164 			"rdinit=/sbin/init enable_wait_mode=off\0" \
165 	"bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
166 			"mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
167 	"bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
168 	"bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
169 			"run bootargs_upd; " \
170 			"bootm 0x10800000 0x10d00000\0" \
171 	"console=ttymxc0\0" \
172 	"fan=gpio set 92\0" \
173 	"set_con_serial=setenv stdout serial; " \
174 			"setenv stderr serial;\0" \
175 	"set_con_hdmi=setenv stdout serial,vga; " \
176 			"setenv stderr serial,vga;\0" \
177 	"stderr=serial,vga;\0" \
178 	"stdin=serial,usbkbd;\0" \
179 	"stdout=serial,vga;\0"
180 
181 #define CONFIG_BOOTCOMMAND \
182 	"mmc rescan; " \
183 	"if run bootcmd_up1; then " \
184 		"run bootcmd_up2; " \
185 	"else " \
186 		"run bootcmd_mmc; " \
187 	"fi"
188 
189 #endif			       /* __TBS2910_CONFIG_H * */
190