1 /* 2 * Copyright (C) 2014 Soeren Moch <smoch@web.de> 3 * 4 * Configuration settings for the TBS2910 MatrixARM board. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __TBS2910_CONFIG_H 10 #define __TBS2910_CONFIG_H 11 12 #include "mx6_common.h" 13 14 /* General configuration */ 15 #define CONFIG_SYS_THUMB_BUILD 16 17 #define CONFIG_MACH_TYPE 3980 18 19 #define CONFIG_BOARD_EARLY_INIT_F 20 21 #define CONFIG_SYS_LONGHELP 22 #define CONFIG_SYS_HUSH_PARSER 23 #define CONFIG_SYS_PROMPT "Matrix U-Boot> " 24 #define CONFIG_BOOTDELAY 3 25 #define CONFIG_AUTO_COMPLETE 26 #define CONFIG_CMDLINE_EDITING 27 #define CONFIG_SYS_MAXARGS 16 28 #define CONFIG_SYS_CBSIZE 1024 29 #define CONFIG_SYS_HZ 1000 30 31 /* Physical Memory Map */ 32 #define CONFIG_NR_DRAM_BANKS 1 33 #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR 34 35 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 36 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 37 #define CONFIG_SYS_INIT_SP_OFFSET \ 38 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 39 #define CONFIG_SYS_INIT_SP_ADDR \ 40 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 41 42 #define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) 43 44 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 45 #define CONFIG_SYS_MEMTEST_END \ 46 (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024) 47 48 #define CONFIG_SYS_TEXT_BASE 0x80000000 49 #define CONFIG_SYS_BOOTMAPSZ 0x6C000000 50 #define CONFIG_SYS_LOAD_ADDR 0x10800000 51 52 /* Serial console */ 53 #define CONFIG_MXC_UART 54 #define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ 55 #define CONFIG_BAUDRATE 115200 56 57 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 58 #define CONFIG_CONSOLE_MUX 59 #define CONFIG_CONS_INDEX 1 60 61 /* *** Command definition *** */ 62 #define CONFIG_CMD_BMODE 63 #define CONFIG_CMD_SETEXPR 64 #define CONFIG_CMD_MEMTEST 65 #define CONFIG_CMD_TIME 66 67 /* Filesystems / image support */ 68 #define CONFIG_CMD_EXT4 69 #define CONFIG_CMD_FAT 70 #define CONFIG_DOS_PARTITION 71 #define CONFIG_EFI_PARTITION 72 #define CONFIG_CMD_FS_GENERIC 73 74 #define CONFIG_OF_LIBFDT 75 #define CONFIG_CMD_BOOTZ 76 #define CONFIG_SUPPORT_RAW_INITRD 77 #define CONFIG_FIT 78 79 /* MMC */ 80 #define CONFIG_FSL_ESDHC 81 #define CONFIG_FSL_USDHC 82 #define CONFIG_SYS_FSL_USDHC_NUM 3 83 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR 84 85 #define CONFIG_MMC 86 #define CONFIG_CMD_MMC 87 #define CONFIG_GENERIC_MMC 88 #define CONFIG_SUPPORT_EMMC_BOOT 89 #define CONFIG_BOUNCE_BUFFER 90 91 /* Ethernet */ 92 #define CONFIG_FEC_MXC 93 #define CONFIG_CMD_PING 94 #define CONFIG_CMD_DHCP 95 #define CONFIG_CMD_MII 96 #define CONFIG_CMD_NET 97 #define CONFIG_FEC_MXC 98 #define CONFIG_MII 99 #define IMX_FEC_BASE ENET_BASE_ADDR 100 #define CONFIG_FEC_XCV_TYPE RGMII 101 #define CONFIG_ETHPRIME "FEC" 102 #define CONFIG_FEC_MXC_PHYADDR 4 103 #define CONFIG_PHYLIB 104 #define CONFIG_PHY_ATHEROS 105 106 /* Framebuffer */ 107 #define CONFIG_VIDEO 108 #ifdef CONFIG_VIDEO 109 #define CONFIG_VIDEO_IPUV3 110 #define CONFIG_IPUV3_CLK 260000000 111 #define CONFIG_CFB_CONSOLE 112 #define CONFIG_CFB_CONSOLE_ANSI 113 #define CONFIG_VIDEO_SW_CURSOR 114 #define CONFIG_VGA_AS_SINGLE_DEVICE 115 #define CONFIG_VIDEO_BMP_RLE8 116 #define CONFIG_IMX_HDMI 117 #define CONFIG_IMX_VIDEO_SKIP 118 #define CONFIG_CMD_HDMIDETECT 119 #endif 120 121 /* PCI */ 122 #define CONFIG_CMD_PCI 123 #ifdef CONFIG_CMD_PCI 124 #define CONFIG_PCI 125 #define CONFIG_PCI_PNP 126 #define CONFIG_PCI_SCAN_SHOW 127 #define CONFIG_PCIE_IMX 128 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) 129 #endif 130 131 /* SATA */ 132 #define CONFIG_CMD_SATA 133 #ifdef CONFIG_CMD_SATA 134 #define CONFIG_DWC_AHSATA 135 #define CONFIG_SYS_SATA_MAX_DEVICE 1 136 #define CONFIG_DWC_AHSATA_PORT_ID 0 137 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 138 #define CONFIG_LBA48 139 #define CONFIG_LIBATA 140 #endif 141 142 /* USB */ 143 #define CONFIG_CMD_USB 144 #ifdef CONFIG_CMD_USB 145 #define CONFIG_USB_EHCI 146 #define CONFIG_USB_EHCI_MX6 147 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 148 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 149 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 150 #define CONFIG_USB_STORAGE 151 #define CONFIG_CMD_USB_MASS_STORAGE 152 #ifdef CONFIG_CMD_USB_MASS_STORAGE 153 #define CONFIG_CI_UDC 154 #define CONFIG_USBD_HS 155 #define CONFIG_USB_GADGET 156 #define CONFIG_USB_GADGET_MASS_STORAGE 157 #define CONFIG_USB_GADGET_DUALSPEED 158 #define CONFIG_USB_GADGET_VBUS_DRAW 0 159 #define CONFIG_USBDOWNLOAD_GADGET 160 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 161 #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 162 #define CONFIG_G_DNL_MANUFACTURER "TBS" 163 #endif /* CONFIG_CMD_USB_MASS_STORAGE */ 164 #define CONFIG_USB_KEYBOARD 165 #ifdef CONFIG_USB_KEYBOARD 166 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE 167 #define CONFIG_SYS_STDIO_DEREGISTER 168 #define CONFIG_PREBOOT \ 169 "if hdmidet; then " \ 170 "usb start; " \ 171 "run set_con_usb_hdmi; " \ 172 "else " \ 173 "run set_con_serial; " \ 174 "fi;" 175 #endif /* CONFIG_USB_KEYBOARD */ 176 #endif /* CONFIG_CMD_USB */ 177 178 /* RTC */ 179 #define CONFIG_CMD_DATE 180 #ifdef CONFIG_CMD_DATE 181 #define CONFIG_CMD_I2C 182 #define CONFIG_RTC_DS1307 183 #define CONFIG_SYS_RTC_BUS_NUM 2 184 #endif 185 186 /* I2C */ 187 #define CONFIG_CMD_I2C 188 #ifdef CONFIG_CMD_I2C 189 #define CONFIG_SYS_I2C 190 #define CONFIG_SYS_I2C_MXC 191 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 192 #define CONFIG_SYS_I2C_SPEED 100000 193 #define CONFIG_I2C_EDID 194 #endif 195 196 /* Fuses */ 197 #define CONFIG_CMD_FUSE 198 #ifdef CONFIG_CMD_FUSE 199 #define CONFIG_MXC_OCOTP 200 #endif 201 202 #ifndef CONFIG_SYS_DCACHE_OFF 203 #define CONFIG_CMD_CACHE 204 #endif 205 206 /* Environment organization */ 207 #define CONFIG_ENV_IS_IN_MMC 208 #define CONFIG_SYS_MMC_ENV_DEV 2 209 #define CONFIG_SYS_MMC_ENV_PART 1 210 #define CONFIG_ENV_SIZE (8 * 1024) 211 #define CONFIG_ENV_OFFSET (384 * 1024) 212 #define CONFIG_ENV_OVERWRITE 213 214 #define CONFIG_EXTRA_ENV_SETTINGS \ 215 "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ 216 "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ 217 "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \ 218 "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \ 219 "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \ 220 "${bootargs_mmc3}\0" \ 221 "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \ 222 "rdinit=/sbin/init enable_wait_mode=off\0" \ 223 "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \ 224 "mmc read 0x10800000 0x800 0x4000; bootm\0" \ 225 "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \ 226 "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \ 227 "run bootargs_upd; " \ 228 "bootm 0x10800000 0x10d00000\0" \ 229 "console=ttymxc0\0" \ 230 "fan=gpio set 92\0" \ 231 "set_con_serial=setenv stdin serial; " \ 232 "setenv stdout serial; " \ 233 "setenv stderr serial;\0" \ 234 "set_con_usb_hdmi=setenv stdin serial,usbkbd; " \ 235 "setenv stdout serial,vga; " \ 236 "setenv stderr serial,vga;\0" 237 238 #define CONFIG_BOOTCOMMAND \ 239 "mmc rescan; " \ 240 "if run bootcmd_up1; then " \ 241 "run bootcmd_up2; " \ 242 "else " \ 243 "run bootcmd_mmc; " \ 244 "fi" 245 246 #endif /* __TBS2910_CONFIG_H * */ 247