1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ 18 #define CONFIG_OMAP /* in a TI OMAP core */ 19 #define CONFIG_OMAP34XX /* which is a 34XX */ 20 21 #define CONFIG_OMAP_GPIO 22 #define CONFIG_OMAP_COMMON 23 24 #define MACH_TYPE_OMAP3_TAO3530 2836 25 26 #define CONFIG_SDRC /* Has an SDRC controller */ 27 28 #include <asm/arch/cpu.h> /* get chip and board defs */ 29 #include <asm/arch/omap3.h> 30 31 /* 32 * Display CPU and Board information 33 */ 34 #define CONFIG_DISPLAY_CPUINFO 35 #define CONFIG_DISPLAY_BOARDINFO 36 37 /* Clock Defines */ 38 #define V_OSCK 26000000 /* Clock output from T2 */ 39 #define V_SCLK (V_OSCK >> 1) 40 41 #define CONFIG_MISC_INIT_R 42 43 #define CONFIG_OF_LIBFDT 44 45 #define CONFIG_CMDLINE_TAG 46 #define CONFIG_SETUP_MEMORY_TAGS 47 #define CONFIG_INITRD_TAG 48 #define CONFIG_REVISION_TAG 49 50 /* 51 * Size of malloc() pool 52 */ 53 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 54 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 55 56 /* 57 * Hardware drivers 58 */ 59 60 /* 61 * NS16550 Configuration 62 */ 63 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 64 65 #define CONFIG_SYS_NS16550 66 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 69 70 /* 71 * select serial console configuration 72 */ 73 #define CONFIG_CONS_INDEX 3 74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 75 76 /* allow to overwrite serial and ethaddr */ 77 #define CONFIG_ENV_OVERWRITE 78 #define CONFIG_BAUDRATE 115200 79 #define CONFIG_GENERIC_MMC 80 #define CONFIG_MMC 81 #define CONFIG_OMAP_HSMMC 82 #define CONFIG_DOS_PARTITION 83 84 /* commands to include */ 85 #include <config_cmd_default.h> 86 87 #define CONFIG_CMD_CACHE 88 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 89 #define CONFIG_CMD_FAT /* FAT support */ 90 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 91 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 92 #define MTDIDS_DEFAULT "nand0=nand" 93 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 94 "1920k(u-boot),128k(u-boot-env),"\ 95 "4m(kernel),-(fs)" 96 97 #define CONFIG_CMD_I2C /* I2C serial bus support */ 98 #define CONFIG_CMD_MMC /* MMC support */ 99 #define CONFIG_CMD_NAND /* NAND support */ 100 #define CONFIG_CMD_DHCP 101 #define CONFIG_CMD_PING 102 103 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 104 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 105 #undef CONFIG_CMD_IMI /* iminfo */ 106 #undef CONFIG_CMD_IMLS /* List all found images */ 107 108 #define CONFIG_SYS_NO_FLASH 109 #define CONFIG_SYS_I2C 110 #define CONFIG_SYS_I2C_OMAP34XX 111 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 112 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 113 #define CONFIG_I2C_MULTI_BUS 114 115 /* 116 * TWL4030 117 */ 118 #define CONFIG_TWL4030_POWER 119 #define CONFIG_TWL4030_LED 120 121 /* 122 * Board NAND Info. 123 */ 124 #define CONFIG_SYS_NAND_QUIET_TEST 125 #define CONFIG_NAND_OMAP_GPMC 126 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 127 /* to access nand */ 128 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 129 /* to access nand at */ 130 /* CS0 */ 131 #define GPMC_NAND_ECC_LP_x16_LAYOUT 132 133 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 134 /* devices */ 135 /* Environment information */ 136 #define CONFIG_BOOTDELAY 3 137 138 #define CONFIG_EXTRA_ENV_SETTINGS \ 139 "loadaddr=0x82000000\0" \ 140 "console=ttyO2,115200n8\0" \ 141 "mpurate=600\0" \ 142 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 143 "tv_mode=omapfb.mode=tv:ntsc\0" \ 144 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 145 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 146 "extra_options= \0" \ 147 "mem_size=mem=128M \0" \ 148 "mmcdev=0\0" \ 149 "mmcroot=/dev/mmcblk0p2 rw\0" \ 150 "mmcrootfstype=ext3 rootwait\0" \ 151 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 152 "nandrootfstype=ubifs\0" \ 153 "mmcargs=setenv bootargs console=${console} " \ 154 "${mem_size} " \ 155 "mpurate=${mpurate} " \ 156 "${video_mode} " \ 157 "root=${mmcroot} " \ 158 "rootfstype=${mmcrootfstype} " \ 159 "${extra_options}\0" \ 160 "nandargs=setenv bootargs console=${console} " \ 161 "${mem_size} " \ 162 "mpurate=${mpurate} " \ 163 "${video_mode} " \ 164 "${network_setting} " \ 165 "root=${nandroot} " \ 166 "rootfstype=${nandrootfstype} "\ 167 "${extra_options}\0" \ 168 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 169 "bootscript=echo Running bootscript from mmc ...; " \ 170 "source ${loadaddr}\0" \ 171 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 172 "mmcboot=echo Booting from mmc ...; " \ 173 "run mmcargs; " \ 174 "bootm ${loadaddr}\0" \ 175 "nandboot=echo Booting from nand ...; " \ 176 "run nandargs; " \ 177 "nand read ${loadaddr} 280000 400000; " \ 178 "bootm ${loadaddr}\0" \ 179 180 #define CONFIG_BOOTCOMMAND \ 181 "if mmc rescan ${mmcdev}; then " \ 182 "if run loadbootscript; then " \ 183 "run bootscript; " \ 184 "else " \ 185 "if run loaduimage; then " \ 186 "run mmcboot; " \ 187 "else run nandboot; " \ 188 "fi; " \ 189 "fi; " \ 190 "else run nandboot; fi" 191 192 /* 193 * Miscellaneous configurable options 194 */ 195 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 196 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 197 #define CONFIG_SYS_PROMPT "TAO-3530 # " 198 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 199 200 /* turn on command-line edit/hist/auto */ 201 #define CONFIG_CMDLINE_EDITING 202 #define CONFIG_COMMAND_HISTORY 203 #define CONFIG_AUTO_COMPLETE 204 205 /* Print Buffer Size */ 206 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 207 sizeof(CONFIG_SYS_PROMPT) + 16) 208 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 209 /* Boot Argument Buffer Size */ 210 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 211 212 #define CONFIG_SYS_ALT_MEMTEST 1 213 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 214 /* defaults */ 215 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 216 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 217 218 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 219 /* load address */ 220 #define CONFIG_SYS_TEXT_BASE 0x80008000 221 222 /* 223 * OMAP3 has 12 GP timers, they can be driven by the system clock 224 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 225 * This rate is divided by a local divisor. 226 */ 227 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 228 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 229 230 /* 231 * Stack sizes 232 * 233 * The stack sizes are set up in start.S using the settings below 234 */ 235 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 236 237 /* 238 * Physical Memory Map 239 */ 240 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 241 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 242 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 243 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 244 245 /* 246 * FLASH and environment organization 247 */ 248 249 /* **** PISMO SUPPORT *** */ 250 251 /* Configure the PISMO */ 252 #define PISMO1_NAND_SIZE GPMC_SIZE_128M 253 #define PISMO1_ONEN_SIZE GPMC_SIZE_128M 254 255 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 256 #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE 257 258 /* Monitor at start of flash */ 259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 260 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 261 262 #define CONFIG_ENV_IS_IN_NAND 1 263 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 264 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 265 266 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 267 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 268 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 269 270 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 271 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 272 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 273 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 274 CONFIG_SYS_INIT_RAM_SIZE - \ 275 GENERATED_GBL_DATA_SIZE) 276 277 #define CONFIG_OMAP3_SPI 278 279 /* 280 * USB 281 * 282 * Currently only EHCI is enabled, the MUSB OTG controller 283 * is not enabled. 284 */ 285 286 /* USB EHCI */ 287 #define CONFIG_CMD_USB 288 #define CONFIG_USB_EHCI 289 #define CONFIG_USB_EHCI_OMAP 290 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 291 292 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 293 #define CONFIG_USB_HOST_ETHER 294 #define CONFIG_USB_ETHER_SMSC95XX 295 296 #define CONFIG_USB_ETHER 297 #define CONFIG_USB_ETHER_RNDIS 298 #define CONFIG_USB_STORAGE 299 #define CONGIG_CMD_STORAGE 300 301 #endif /* __CONFIG_H */ 302