1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 20 #define CONFIG_SDRC /* Has an SDRC controller */ 21 22 #include <asm/arch/cpu.h> /* get chip and board defs */ 23 #include <asm/arch/omap.h> 24 25 /* Clock Defines */ 26 #define V_OSCK 26000000 /* Clock output from T2 */ 27 #define V_SCLK (V_OSCK >> 1) 28 29 #define CONFIG_MISC_INIT_R 30 31 #define CONFIG_CMDLINE_TAG 32 #define CONFIG_SETUP_MEMORY_TAGS 33 #define CONFIG_INITRD_TAG 34 #define CONFIG_REVISION_TAG 35 36 /* 37 * Size of malloc() pool 38 */ 39 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 40 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 41 42 /* 43 * Hardware drivers 44 */ 45 46 /* 47 * NS16550 Configuration 48 */ 49 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 50 51 #define CONFIG_SYS_NS16550_SERIAL 52 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 53 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 54 55 /* 56 * select serial console configuration 57 */ 58 #define CONFIG_CONS_INDEX 3 59 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 60 61 /* allow to overwrite serial and ethaddr */ 62 #define CONFIG_ENV_OVERWRITE 63 64 /* GPIO banks */ 65 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 66 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 67 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 68 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 69 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 70 71 /* commands to include */ 72 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 73 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 74 #define MTDIDS_DEFAULT "nand0=nand" 75 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 76 "1920k(u-boot),128k(u-boot-env),"\ 77 "4m(kernel),-(fs)" 78 79 #define CONFIG_CMD_NAND /* NAND support */ 80 81 #define CONFIG_SYS_I2C 82 #define CONFIG_SYS_I2C_OMAP34XX 83 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 84 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 85 #define CONFIG_I2C_MULTI_BUS 86 87 /* 88 * TWL4030 89 */ 90 #define CONFIG_TWL4030_LED 91 92 /* 93 * Board NAND Info. 94 */ 95 #define CONFIG_NAND_OMAP_GPMC 96 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 97 /* to access nand */ 98 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 99 /* to access nand at */ 100 /* CS0 */ 101 102 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 103 /* devices */ 104 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 105 /* Environment information */ 106 107 #define CONFIG_EXTRA_ENV_SETTINGS \ 108 "loadaddr=0x82000000\0" \ 109 "console=ttyO2,115200n8\0" \ 110 "mpurate=600\0" \ 111 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 112 "tv_mode=omapfb.mode=tv:ntsc\0" \ 113 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 114 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 115 "extra_options= \0" \ 116 "mmcdev=0\0" \ 117 "mmcroot=/dev/mmcblk0p2 rw\0" \ 118 "mmcrootfstype=ext3 rootwait\0" \ 119 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 120 "nandrootfstype=ubifs\0" \ 121 "mmcargs=setenv bootargs console=${console} " \ 122 "mpurate=${mpurate} " \ 123 "${video_mode} " \ 124 "root=${mmcroot} " \ 125 "rootfstype=${mmcrootfstype} " \ 126 "${extra_options}\0" \ 127 "nandargs=setenv bootargs console=${console} " \ 128 "mpurate=${mpurate} " \ 129 "${video_mode} " \ 130 "${network_setting} " \ 131 "root=${nandroot} " \ 132 "rootfstype=${nandrootfstype} "\ 133 "${extra_options}\0" \ 134 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 135 "bootscript=echo Running bootscript from mmc ...; " \ 136 "source ${loadaddr}\0" \ 137 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 138 "mmcboot=echo Booting from mmc ...; " \ 139 "run mmcargs; " \ 140 "bootm ${loadaddr}\0" \ 141 "nandboot=echo Booting from nand ...; " \ 142 "run nandargs; " \ 143 "nand read ${loadaddr} 280000 400000; " \ 144 "bootm ${loadaddr}\0" \ 145 146 #define CONFIG_BOOTCOMMAND \ 147 "if mmc rescan ${mmcdev}; then " \ 148 "if run loadbootscript; then " \ 149 "run bootscript; " \ 150 "else " \ 151 "if run loaduimage; then " \ 152 "run mmcboot; " \ 153 "else run nandboot; " \ 154 "fi; " \ 155 "fi; " \ 156 "else run nandboot; fi" 157 158 /* 159 * Miscellaneous configurable options 160 */ 161 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 162 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 163 164 /* turn on command-line edit/hist/auto */ 165 #define CONFIG_CMDLINE_EDITING 166 #define CONFIG_AUTO_COMPLETE 167 168 /* Print Buffer Size */ 169 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 170 sizeof(CONFIG_SYS_PROMPT) + 16) 171 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 172 /* Boot Argument Buffer Size */ 173 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 174 175 #define CONFIG_SYS_ALT_MEMTEST 1 176 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 177 /* defaults */ 178 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 179 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 180 181 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 182 /* load address */ 183 #define CONFIG_SYS_TEXT_BASE 0x80008000 184 185 /* 186 * OMAP3 has 12 GP timers, they can be driven by the system clock 187 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 188 * This rate is divided by a local divisor. 189 */ 190 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 191 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 192 193 /* 194 * Physical Memory Map 195 */ 196 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 197 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 198 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 199 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 200 201 /* 202 * FLASH and environment organization 203 */ 204 205 /* **** PISMO SUPPORT *** */ 206 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 207 #define CONFIG_SYS_FLASH_BASE NAND_BASE 208 209 /* Monitor at start of flash */ 210 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 211 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 212 213 #define CONFIG_ENV_IS_IN_NAND 1 214 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 215 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 216 217 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 218 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 219 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 220 221 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 222 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 223 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 224 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 225 CONFIG_SYS_INIT_RAM_SIZE - \ 226 GENERATED_GBL_DATA_SIZE) 227 228 #define CONFIG_OMAP3_SPI 229 230 /* 231 * USB 232 * 233 * Currently only EHCI is enabled, the MUSB OTG controller 234 * is not enabled. 235 */ 236 237 /* USB EHCI */ 238 #define CONFIG_USB_EHCI 239 #define CONFIG_USB_EHCI_OMAP 240 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 241 242 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 243 #define CONFIG_USB_HOST_ETHER 244 #define CONFIG_USB_ETHER_SMSC95XX 245 246 #define CONFIG_USB_ETHER 247 #define CONFIG_USB_ETHER_RNDIS 248 249 /* Defines for SPL */ 250 #define CONFIG_SPL_FRAMEWORK 251 #define CONFIG_SPL_NAND_SIMPLE 252 253 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 254 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 255 256 #define CONFIG_SPL_BOARD_INIT 257 #define CONFIG_SPL_NAND_BASE 258 #define CONFIG_SPL_NAND_DRIVERS 259 #define CONFIG_SPL_NAND_ECC 260 #define CONFIG_SPL_OMAP3_ID_NAND 261 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 262 263 /* NAND boot config */ 264 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 265 #define CONFIG_SYS_NAND_PAGE_COUNT 64 266 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 267 #define CONFIG_SYS_NAND_OOBSIZE 64 268 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 269 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 270 /* 271 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 272 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 273 */ 274 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 275 10, 11, 12, 13 } 276 #define CONFIG_SYS_NAND_ECCSIZE 512 277 #define CONFIG_SYS_NAND_ECCBYTES 3 278 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 279 280 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 281 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 282 283 #define CONFIG_SPL_TEXT_BASE 0x40200800 284 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 285 CONFIG_SPL_TEXT_BASE) 286 287 /* 288 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 289 * older x-loader implementations. And move the BSS area so that it 290 * doesn't overlap with TEXT_BASE. 291 */ 292 #define CONFIG_SYS_TEXT_BASE 0x80008000 293 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 294 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 295 296 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 297 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 298 299 #endif /* __CONFIG_H */ 300