1 /* 2 * Configuration settings for the TechNexion TAO-3530 SOM 3 * equipped on Thunder baseboard. 4 * 5 * Edward Lin <linuxfae@technexion.com> 6 * Tapani Utriainen <linuxfae@technexion.com> 7 * 8 * Copyright (C) 2013 Stefan Roese <sr@denx.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP /* in a TI OMAP core */ 20 21 #define CONFIG_OMAP_GPIO 22 #define CONFIG_OMAP_COMMON 23 /* Common ARM Erratas */ 24 #define CONFIG_ARM_ERRATA_454179 25 #define CONFIG_ARM_ERRATA_430973 26 #define CONFIG_ARM_ERRATA_621766 27 28 #define MACH_TYPE_OMAP3_TAO3530 2836 29 30 #define CONFIG_SDRC /* Has an SDRC controller */ 31 32 #include <asm/arch/cpu.h> /* get chip and board defs */ 33 #include <asm/arch/omap.h> 34 35 /* 36 * Display CPU and Board information 37 */ 38 #define CONFIG_DISPLAY_BOARDINFO 39 40 /* Clock Defines */ 41 #define V_OSCK 26000000 /* Clock output from T2 */ 42 #define V_SCLK (V_OSCK >> 1) 43 44 #define CONFIG_MISC_INIT_R 45 46 #define CONFIG_CMDLINE_TAG 47 #define CONFIG_SETUP_MEMORY_TAGS 48 #define CONFIG_INITRD_TAG 49 #define CONFIG_REVISION_TAG 50 51 /* 52 * Size of malloc() pool 53 */ 54 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 55 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 56 57 /* 58 * Hardware drivers 59 */ 60 61 /* 62 * NS16550 Configuration 63 */ 64 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 65 66 #define CONFIG_SYS_NS16550_SERIAL 67 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 69 70 /* 71 * select serial console configuration 72 */ 73 #define CONFIG_CONS_INDEX 3 74 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 75 76 /* allow to overwrite serial and ethaddr */ 77 #define CONFIG_ENV_OVERWRITE 78 #define CONFIG_BAUDRATE 115200 79 #define CONFIG_GENERIC_MMC 80 #define CONFIG_MMC 81 #define CONFIG_OMAP_HSMMC 82 #define CONFIG_DOS_PARTITION 83 84 /* GPIO banks */ 85 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */ 86 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */ 87 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */ 88 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */ 89 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ 90 91 /* commands to include */ 92 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 93 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 94 #define MTDIDS_DEFAULT "nand0=nand" 95 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 96 "1920k(u-boot),128k(u-boot-env),"\ 97 "4m(kernel),-(fs)" 98 99 #define CONFIG_CMD_NAND /* NAND support */ 100 101 #define CONFIG_SYS_NO_FLASH 102 #define CONFIG_SYS_I2C 103 #define CONFIG_SYS_I2C_OMAP34XX 104 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 105 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 106 #define CONFIG_I2C_MULTI_BUS 107 108 /* 109 * TWL4030 110 */ 111 #define CONFIG_TWL4030_POWER 112 #define CONFIG_TWL4030_LED 113 114 /* 115 * Board NAND Info. 116 */ 117 #define CONFIG_NAND_OMAP_GPMC 118 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 119 /* to access nand */ 120 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 121 /* to access nand at */ 122 /* CS0 */ 123 124 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 125 /* devices */ 126 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 127 /* Environment information */ 128 129 #define CONFIG_EXTRA_ENV_SETTINGS \ 130 "loadaddr=0x82000000\0" \ 131 "console=ttyO2,115200n8\0" \ 132 "mpurate=600\0" \ 133 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ 134 "tv_mode=omapfb.mode=tv:ntsc\0" \ 135 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ 136 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ 137 "extra_options= \0" \ 138 "mmcdev=0\0" \ 139 "mmcroot=/dev/mmcblk0p2 rw\0" \ 140 "mmcrootfstype=ext3 rootwait\0" \ 141 "nandroot=ubi0:rootfs ubi.mtd=4\0" \ 142 "nandrootfstype=ubifs\0" \ 143 "mmcargs=setenv bootargs console=${console} " \ 144 "mpurate=${mpurate} " \ 145 "${video_mode} " \ 146 "root=${mmcroot} " \ 147 "rootfstype=${mmcrootfstype} " \ 148 "${extra_options}\0" \ 149 "nandargs=setenv bootargs console=${console} " \ 150 "mpurate=${mpurate} " \ 151 "${video_mode} " \ 152 "${network_setting} " \ 153 "root=${nandroot} " \ 154 "rootfstype=${nandrootfstype} "\ 155 "${extra_options}\0" \ 156 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 157 "bootscript=echo Running bootscript from mmc ...; " \ 158 "source ${loadaddr}\0" \ 159 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 160 "mmcboot=echo Booting from mmc ...; " \ 161 "run mmcargs; " \ 162 "bootm ${loadaddr}\0" \ 163 "nandboot=echo Booting from nand ...; " \ 164 "run nandargs; " \ 165 "nand read ${loadaddr} 280000 400000; " \ 166 "bootm ${loadaddr}\0" \ 167 168 #define CONFIG_BOOTCOMMAND \ 169 "if mmc rescan ${mmcdev}; then " \ 170 "if run loadbootscript; then " \ 171 "run bootscript; " \ 172 "else " \ 173 "if run loaduimage; then " \ 174 "run mmcboot; " \ 175 "else run nandboot; " \ 176 "fi; " \ 177 "fi; " \ 178 "else run nandboot; fi" 179 180 /* 181 * Miscellaneous configurable options 182 */ 183 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 184 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 185 186 /* turn on command-line edit/hist/auto */ 187 #define CONFIG_CMDLINE_EDITING 188 #define CONFIG_COMMAND_HISTORY 189 #define CONFIG_AUTO_COMPLETE 190 191 /* Print Buffer Size */ 192 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 193 sizeof(CONFIG_SYS_PROMPT) + 16) 194 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 195 /* Boot Argument Buffer Size */ 196 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 197 198 #define CONFIG_SYS_ALT_MEMTEST 1 199 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ 200 /* defaults */ 201 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ 202 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ 203 204 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ 205 /* load address */ 206 #define CONFIG_SYS_TEXT_BASE 0x80008000 207 208 /* 209 * OMAP3 has 12 GP timers, they can be driven by the system clock 210 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 211 * This rate is divided by a local divisor. 212 */ 213 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 214 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 215 216 /* 217 * Stack sizes 218 * 219 * The stack sizes are set up in start.S using the settings below 220 */ 221 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 222 223 /* 224 * Physical Memory Map 225 */ 226 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 227 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 228 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 229 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 230 231 /* 232 * FLASH and environment organization 233 */ 234 235 /* **** PISMO SUPPORT *** */ 236 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 237 #define CONFIG_SYS_FLASH_BASE NAND_BASE 238 239 /* Monitor at start of flash */ 240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 241 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 242 243 #define CONFIG_ENV_IS_IN_NAND 1 244 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 245 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 246 247 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) 248 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 249 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 250 251 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 252 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 253 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 254 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 255 CONFIG_SYS_INIT_RAM_SIZE - \ 256 GENERATED_GBL_DATA_SIZE) 257 258 #define CONFIG_OMAP3_SPI 259 260 /* 261 * USB 262 * 263 * Currently only EHCI is enabled, the MUSB OTG controller 264 * is not enabled. 265 */ 266 267 /* USB EHCI */ 268 #define CONFIG_USB_EHCI 269 #define CONFIG_USB_EHCI_OMAP 270 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 271 272 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 273 #define CONFIG_USB_HOST_ETHER 274 #define CONFIG_USB_ETHER_SMSC95XX 275 276 #define CONFIG_USB_ETHER 277 #define CONFIG_USB_ETHER_RNDIS 278 #define CONGIG_CMD_STORAGE 279 280 /* Defines for SPL */ 281 #define CONFIG_SPL_FRAMEWORK 282 #define CONFIG_SPL_NAND_SIMPLE 283 284 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ 285 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ 286 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 287 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 288 289 #define CONFIG_SPL_BOARD_INIT 290 #define CONFIG_SPL_NAND_BASE 291 #define CONFIG_SPL_NAND_DRIVERS 292 #define CONFIG_SPL_NAND_ECC 293 #define CONFIG_SPL_OMAP3_ID_NAND 294 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 295 296 /* NAND boot config */ 297 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 298 #define CONFIG_SYS_NAND_PAGE_COUNT 64 299 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 300 #define CONFIG_SYS_NAND_OOBSIZE 64 301 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 302 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 303 /* 304 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: 305 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT 306 */ 307 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 308 10, 11, 12, 13 } 309 #define CONFIG_SYS_NAND_ECCSIZE 512 310 #define CONFIG_SYS_NAND_ECCBYTES 3 311 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 312 313 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 314 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 315 316 #define CONFIG_SPL_TEXT_BASE 0x40200800 317 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 318 CONFIG_SPL_TEXT_BASE) 319 320 /* 321 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the 322 * older x-loader implementations. And move the BSS area so that it 323 * doesn't overlap with TEXT_BASE. 324 */ 325 #define CONFIG_SYS_TEXT_BASE 0x80008000 326 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 327 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 328 329 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 330 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 331 332 #endif /* __CONFIG_H */ 333