1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP_GPIO 17 18 #define CONFIG_SYS_TEXT_BASE 0x80008000 19 20 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 21 22 #include <asm/arch/cpu.h> /* get chip and board defs */ 23 #include <asm/arch/omap.h> 24 25 /* Clock Defines */ 26 #define V_OSCK 26000000 /* Clock output from T2 */ 27 #define V_SCLK (V_OSCK >> 1) 28 29 #define CONFIG_MISC_INIT_R 30 31 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 32 #define CONFIG_SETUP_MEMORY_TAGS 33 #define CONFIG_INITRD_TAG 34 #define CONFIG_REVISION_TAG 35 36 /* 37 * Size of malloc() pool 38 */ 39 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 40 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 41 2 * 1024 * 1024) 42 /* 43 * DDR related 44 */ 45 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 46 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 47 48 /* 49 * Hardware drivers 50 */ 51 52 /* 53 * NS16550 Configuration 54 */ 55 #define CONFIG_SYS_NS16550_SERIAL 56 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 57 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 58 59 /* 60 * select serial console configuration 61 */ 62 #define CONFIG_CONS_INDEX 1 63 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 64 #define CONFIG_SERIAL1 /* UART1 */ 65 66 /* allow to overwrite serial and ethaddr */ 67 #define CONFIG_ENV_OVERWRITE 68 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 69 115200} 70 /* EHCI */ 71 #define CONFIG_OMAP3_GPIO_5 72 #define CONFIG_USB_EHCI 73 #define CONFIG_USB_EHCI_OMAP 74 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 75 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 76 77 /* commands to include */ 78 #define CONFIG_CMD_NAND /* NAND support */ 79 #define CONFIG_CMD_EEPROM 80 81 #define CONFIG_SYS_I2C 82 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 83 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 84 #define CONFIG_SYS_I2C_OMAP34XX 85 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 86 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 87 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 88 89 /* 90 * Board NAND Info. 91 */ 92 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 93 /* to access */ 94 /* nand at CS0 */ 95 96 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 97 /* NAND devices */ 98 99 #define CONFIG_AUTO_COMPLETE 100 101 /* 102 * Miscellaneous configurable options 103 */ 104 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 105 #define CONFIG_CMDLINE_EDITING 106 #define CONFIG_AUTO_COMPLETE 107 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 108 109 /* Print Buffer Size */ 110 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 111 sizeof(CONFIG_SYS_PROMPT) + 16) 112 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 113 /* args */ 114 /* Boot Argument Buffer Size */ 115 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 116 /* memtest works on */ 117 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 118 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 119 0x01F00000) /* 31MB */ 120 121 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 122 /* address */ 123 124 /* 125 * AM3517 has 12 GP timers, they can be driven by the system clock 126 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 127 * This rate is divided by a local divisor. 128 */ 129 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 130 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 131 132 /* 133 * Physical Memory Map 134 */ 135 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 136 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 137 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 138 139 /* 140 * FLASH and environment organization 141 */ 142 143 /* **** PISMO SUPPORT *** */ 144 #define CONFIG_NAND 145 #define CONFIG_NAND_OMAP_GPMC 146 #define CONFIG_ENV_IS_IN_NAND 147 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 148 149 /* Redundant Environment */ 150 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 151 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 152 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 153 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 154 2 * CONFIG_SYS_ENV_SECT_SIZE) 155 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 156 157 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 158 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 159 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 160 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 161 CONFIG_SYS_INIT_RAM_SIZE - \ 162 GENERATED_GBL_DATA_SIZE) 163 164 /* 165 * ethernet support, EMAC 166 * 167 */ 168 #define CONFIG_DRIVER_TI_EMAC 169 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 170 #define CONFIG_MII 171 #define CONFIG_BOOTP_DNS 172 #define CONFIG_BOOTP_DNS2 173 #define CONFIG_BOOTP_SEND_HOSTNAME 174 #define CONFIG_NET_RETRY_COUNT 10 175 176 /* Defines for SPL */ 177 #define CONFIG_SPL_FRAMEWORK 178 #define CONFIG_SPL_BOARD_INIT 179 #define CONFIG_SPL_CONSOLE 180 #define CONFIG_SPL_NAND_SIMPLE 181 #define CONFIG_SPL_NAND_SOFTECC 182 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 183 184 #define CONFIG_SPL_NAND_BASE 185 #define CONFIG_SPL_NAND_DRIVERS 186 #define CONFIG_SPL_NAND_ECC 187 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 188 189 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 190 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 191 CONFIG_SPL_TEXT_BASE) 192 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 193 194 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 195 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 196 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 197 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 198 199 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 200 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 201 202 /* FAT */ 203 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 204 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 205 206 /* RAW SD card / eMMC */ 207 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 208 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 209 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 210 211 /* NAND boot config */ 212 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 213 #define CONFIG_SYS_NAND_PAGE_COUNT 64 214 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 215 #define CONFIG_SYS_NAND_OOBSIZE 64 216 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 217 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 218 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 219 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 220 48, 49, 50, 51, 52, 53, 54, 55,\ 221 56, 57, 58, 59, 60, 61, 62, 63} 222 #define CONFIG_SYS_NAND_ECCSIZE 256 223 #define CONFIG_SYS_NAND_ECCBYTES 3 224 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 225 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 226 227 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 228 229 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 230 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 231 232 #define CONFIG_CMD_UBIFS 233 #define CONFIG_RBTREE 234 #define CONFIG_LZO 235 #define CONFIG_MTD_PARTITIONS 236 #define CONFIG_MTD_DEVICE 237 #define CONFIG_CMD_MTDPARTS 238 239 /* Setup MTD for NAND on the SOM */ 240 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 241 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 242 "1m(u-boot),256k(env1)," \ 243 "256k(env2),6m(kernel),-(rootfs)" 244 245 #define CONFIG_TAM3517_SETTINGS \ 246 "netdev=eth0\0" \ 247 "nandargs=setenv bootargs root=${nandroot} " \ 248 "rootfstype=${nandrootfstype}\0" \ 249 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 250 "nfsroot=${serverip}:${rootpath}\0" \ 251 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 252 "addip_sta=setenv bootargs ${bootargs} " \ 253 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 254 ":${hostname}:${netdev}:off panic=1\0" \ 255 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 256 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 257 "else run addip_sta;fi\0" \ 258 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 259 "addtty=setenv bootargs ${bootargs}" \ 260 " console=ttyO0,${baudrate}\0" \ 261 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 262 "loadaddr=82000000\0" \ 263 "kernel_addr_r=82000000\0" \ 264 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 265 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 266 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 267 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 268 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 269 "bootm ${kernel_addr}\0" \ 270 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 271 "nand read ${kernel_addr_r} kernel\0" \ 272 "bootm ${kernel_addr_r}\0" \ 273 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 274 "run nfsargs addip addtty addmtd addmisc;" \ 275 "bootm ${kernel_addr_r}\0" \ 276 "net_self=if run net_self_load;then " \ 277 "run ramargs addip addtty addmtd addmisc;" \ 278 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 279 "else echo Images not loades;fi\0" \ 280 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 281 "load=tftp ${loadaddr} ${u-boot}\0" \ 282 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 283 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 284 "uboot_addr=0x80000\0" \ 285 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 286 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 287 "updatemlo=nandecc hw;nand erase 0 20000;" \ 288 "nand write ${loadaddr} 0 20000\0" \ 289 "upd=if run load;then echo Updating u-boot;if run update;" \ 290 "then echo U-Boot updated;" \ 291 "else echo Error updating u-boot !;" \ 292 "echo Board without bootloader !!;" \ 293 "fi;" \ 294 "else echo U-Boot not downloaded..exiting;fi\0" \ 295 296 /* 297 * this is common code for all TAM3517 boards. 298 * MAC address is stored from manufacturer in 299 * I2C EEPROM 300 */ 301 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 302 /* 303 * The I2C EEPROM on the TAM3517 contains 304 * mac address and production data 305 */ 306 struct tam3517_module_info { 307 char customer[48]; 308 char product[48]; 309 310 /* 311 * bit 0~47 : sequence number 312 * bit 48~55 : week of year, from 0. 313 * bit 56~63 : year 314 */ 315 unsigned long long sequence_number; 316 317 /* 318 * bit 0~7 : revision fixed 319 * bit 8~15 : revision major 320 * bit 16~31 : TNxxx 321 */ 322 unsigned int revision; 323 unsigned char eth_addr[4][8]; 324 unsigned char _rev[100]; 325 }; 326 327 #define TAM3517_READ_EEPROM(info, ret) \ 328 do { \ 329 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 330 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 331 (void *)info, sizeof(*info))) \ 332 ret = 1; \ 333 else \ 334 ret = 0; \ 335 } while (0) 336 337 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 338 do { \ 339 char buf[80], ethname[20]; \ 340 int i; \ 341 memset(buf, 0, sizeof(buf)); \ 342 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 343 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 344 (info)->eth_addr[i][5], \ 345 (info)->eth_addr[i][4], \ 346 (info)->eth_addr[i][3], \ 347 (info)->eth_addr[i][2], \ 348 (info)->eth_addr[i][1], \ 349 (info)->eth_addr[i][0]); \ 350 \ 351 if (i) \ 352 sprintf(ethname, "eth%daddr", i); \ 353 else \ 354 strcpy(ethname, "ethaddr"); \ 355 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 356 setenv(ethname, buf); \ 357 } \ 358 } while (0) 359 360 /* The following macros are taken from Technexion's documentation */ 361 #define TAM3517_sequence_number(info) \ 362 ((info)->sequence_number % 0x1000000000000LL) 363 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 364 #define TAM3517_year(info) ((info)->sequence_number >> 56) 365 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 366 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 367 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 368 369 #define TAM3517_PRINT_SOM_INFO(info) \ 370 do { \ 371 printf("Vendor:%s\n", (info)->customer); \ 372 printf("SOM: %s\n", (info)->product); \ 373 printf("SeqNr: %02llu%02llu%012llu\n", \ 374 TAM3517_year(info), \ 375 TAM3517_week_of_year(info), \ 376 TAM3517_sequence_number(info)); \ 377 printf("Rev: TN%u %u.%u\n", \ 378 TAM3517_revision_tn(info), \ 379 TAM3517_revision_major(info), \ 380 TAM3517_revision_fixed(info)); \ 381 } while (0) 382 383 #endif 384 385 #endif /* __TAM3517_H */ 386