1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 17 #define CONFIG_SYS_TEXT_BASE 0x80008000 18 19 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 20 21 #include <asm/arch/cpu.h> /* get chip and board defs */ 22 #include <asm/arch/omap.h> 23 24 /* Clock Defines */ 25 #define V_OSCK 26000000 /* Clock output from T2 */ 26 #define V_SCLK (V_OSCK >> 1) 27 28 #define CONFIG_MISC_INIT_R 29 30 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 31 #define CONFIG_SETUP_MEMORY_TAGS 32 #define CONFIG_INITRD_TAG 33 #define CONFIG_REVISION_TAG 34 35 /* 36 * Size of malloc() pool 37 */ 38 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 39 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 40 2 * 1024 * 1024) 41 /* 42 * DDR related 43 */ 44 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 45 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 46 47 /* 48 * Hardware drivers 49 */ 50 51 /* 52 * NS16550 Configuration 53 */ 54 #define CONFIG_SYS_NS16550_SERIAL 55 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 56 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 57 58 /* 59 * select serial console configuration 60 */ 61 #define CONFIG_CONS_INDEX 1 62 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 63 #define CONFIG_SERIAL1 /* UART1 */ 64 65 /* allow to overwrite serial and ethaddr */ 66 #define CONFIG_ENV_OVERWRITE 67 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 68 115200} 69 /* EHCI */ 70 #define CONFIG_USB_EHCI_OMAP 71 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 72 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 73 74 /* commands to include */ 75 #define CONFIG_CMD_NAND /* NAND support */ 76 #define CONFIG_CMD_EEPROM 77 78 #define CONFIG_SYS_I2C 79 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 80 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 81 #define CONFIG_SYS_I2C_OMAP34XX 82 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 83 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 84 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 85 86 /* 87 * Board NAND Info. 88 */ 89 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 90 /* to access */ 91 /* nand at CS0 */ 92 93 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 94 /* NAND devices */ 95 96 #define CONFIG_AUTO_COMPLETE 97 98 /* 99 * Miscellaneous configurable options 100 */ 101 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 102 #define CONFIG_CMDLINE_EDITING 103 #define CONFIG_AUTO_COMPLETE 104 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 105 106 /* Print Buffer Size */ 107 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 108 sizeof(CONFIG_SYS_PROMPT) + 16) 109 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 110 /* args */ 111 /* Boot Argument Buffer Size */ 112 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 113 /* memtest works on */ 114 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 115 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 116 0x01F00000) /* 31MB */ 117 118 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 119 /* address */ 120 121 /* 122 * AM3517 has 12 GP timers, they can be driven by the system clock 123 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 124 * This rate is divided by a local divisor. 125 */ 126 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 127 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 128 129 /* 130 * Physical Memory Map 131 */ 132 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 133 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 134 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 135 136 /* 137 * FLASH and environment organization 138 */ 139 140 /* **** PISMO SUPPORT *** */ 141 #define CONFIG_NAND 142 #define CONFIG_NAND_OMAP_GPMC 143 #define CONFIG_ENV_IS_IN_NAND 144 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 145 146 /* Redundant Environment */ 147 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 148 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 149 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 150 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 151 2 * CONFIG_SYS_ENV_SECT_SIZE) 152 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 153 154 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 155 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 156 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 157 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 158 CONFIG_SYS_INIT_RAM_SIZE - \ 159 GENERATED_GBL_DATA_SIZE) 160 161 /* 162 * ethernet support, EMAC 163 * 164 */ 165 #define CONFIG_DRIVER_TI_EMAC 166 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 167 #define CONFIG_MII 168 #define CONFIG_BOOTP_DNS 169 #define CONFIG_BOOTP_DNS2 170 #define CONFIG_BOOTP_SEND_HOSTNAME 171 #define CONFIG_NET_RETRY_COUNT 10 172 173 /* Defines for SPL */ 174 #define CONFIG_SPL_FRAMEWORK 175 #define CONFIG_SPL_BOARD_INIT 176 #define CONFIG_SPL_CONSOLE 177 #define CONFIG_SPL_NAND_SIMPLE 178 #define CONFIG_SPL_NAND_SOFTECC 179 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 180 181 #define CONFIG_SPL_NAND_BASE 182 #define CONFIG_SPL_NAND_DRIVERS 183 #define CONFIG_SPL_NAND_ECC 184 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 185 186 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 187 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 188 CONFIG_SPL_TEXT_BASE) 189 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 190 191 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 192 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 193 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 194 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 195 196 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 197 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 198 199 /* FAT */ 200 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 201 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 202 203 /* RAW SD card / eMMC */ 204 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 205 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 206 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 207 208 /* NAND boot config */ 209 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 210 #define CONFIG_SYS_NAND_PAGE_COUNT 64 211 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 212 #define CONFIG_SYS_NAND_OOBSIZE 64 213 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 214 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 215 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 216 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 217 48, 49, 50, 51, 52, 53, 54, 55,\ 218 56, 57, 58, 59, 60, 61, 62, 63} 219 #define CONFIG_SYS_NAND_ECCSIZE 256 220 #define CONFIG_SYS_NAND_ECCBYTES 3 221 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 222 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 223 224 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 225 226 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 227 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 228 229 #define CONFIG_CMD_UBIFS 230 #define CONFIG_RBTREE 231 #define CONFIG_LZO 232 #define CONFIG_MTD_PARTITIONS 233 #define CONFIG_MTD_DEVICE 234 #define CONFIG_CMD_MTDPARTS 235 236 /* Setup MTD for NAND on the SOM */ 237 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 238 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 239 "1m(u-boot),256k(env1)," \ 240 "256k(env2),6m(kernel),-(rootfs)" 241 242 #define CONFIG_TAM3517_SETTINGS \ 243 "netdev=eth0\0" \ 244 "nandargs=setenv bootargs root=${nandroot} " \ 245 "rootfstype=${nandrootfstype}\0" \ 246 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 247 "nfsroot=${serverip}:${rootpath}\0" \ 248 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 249 "addip_sta=setenv bootargs ${bootargs} " \ 250 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 251 ":${hostname}:${netdev}:off panic=1\0" \ 252 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 253 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 254 "else run addip_sta;fi\0" \ 255 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 256 "addtty=setenv bootargs ${bootargs}" \ 257 " console=ttyO0,${baudrate}\0" \ 258 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 259 "loadaddr=82000000\0" \ 260 "kernel_addr_r=82000000\0" \ 261 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 262 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 263 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 264 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 265 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 266 "bootm ${kernel_addr}\0" \ 267 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 268 "nand read ${kernel_addr_r} kernel\0" \ 269 "bootm ${kernel_addr_r}\0" \ 270 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 271 "run nfsargs addip addtty addmtd addmisc;" \ 272 "bootm ${kernel_addr_r}\0" \ 273 "net_self=if run net_self_load;then " \ 274 "run ramargs addip addtty addmtd addmisc;" \ 275 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 276 "else echo Images not loades;fi\0" \ 277 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 278 "load=tftp ${loadaddr} ${u-boot}\0" \ 279 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 280 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 281 "uboot_addr=0x80000\0" \ 282 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 283 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 284 "updatemlo=nandecc hw;nand erase 0 20000;" \ 285 "nand write ${loadaddr} 0 20000\0" \ 286 "upd=if run load;then echo Updating u-boot;if run update;" \ 287 "then echo U-Boot updated;" \ 288 "else echo Error updating u-boot !;" \ 289 "echo Board without bootloader !!;" \ 290 "fi;" \ 291 "else echo U-Boot not downloaded..exiting;fi\0" \ 292 293 /* 294 * this is common code for all TAM3517 boards. 295 * MAC address is stored from manufacturer in 296 * I2C EEPROM 297 */ 298 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 299 /* 300 * The I2C EEPROM on the TAM3517 contains 301 * mac address and production data 302 */ 303 struct tam3517_module_info { 304 char customer[48]; 305 char product[48]; 306 307 /* 308 * bit 0~47 : sequence number 309 * bit 48~55 : week of year, from 0. 310 * bit 56~63 : year 311 */ 312 unsigned long long sequence_number; 313 314 /* 315 * bit 0~7 : revision fixed 316 * bit 8~15 : revision major 317 * bit 16~31 : TNxxx 318 */ 319 unsigned int revision; 320 unsigned char eth_addr[4][8]; 321 unsigned char _rev[100]; 322 }; 323 324 #define TAM3517_READ_EEPROM(info, ret) \ 325 do { \ 326 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 327 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 328 (void *)info, sizeof(*info))) \ 329 ret = 1; \ 330 else \ 331 ret = 0; \ 332 } while (0) 333 334 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 335 do { \ 336 char buf[80], ethname[20]; \ 337 int i; \ 338 memset(buf, 0, sizeof(buf)); \ 339 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 340 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 341 (info)->eth_addr[i][5], \ 342 (info)->eth_addr[i][4], \ 343 (info)->eth_addr[i][3], \ 344 (info)->eth_addr[i][2], \ 345 (info)->eth_addr[i][1], \ 346 (info)->eth_addr[i][0]); \ 347 \ 348 if (i) \ 349 sprintf(ethname, "eth%daddr", i); \ 350 else \ 351 strcpy(ethname, "ethaddr"); \ 352 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 353 setenv(ethname, buf); \ 354 } \ 355 } while (0) 356 357 /* The following macros are taken from Technexion's documentation */ 358 #define TAM3517_sequence_number(info) \ 359 ((info)->sequence_number % 0x1000000000000LL) 360 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 361 #define TAM3517_year(info) ((info)->sequence_number >> 56) 362 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 363 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 364 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 365 366 #define TAM3517_PRINT_SOM_INFO(info) \ 367 do { \ 368 printf("Vendor:%s\n", (info)->customer); \ 369 printf("SOM: %s\n", (info)->product); \ 370 printf("SeqNr: %02llu%02llu%012llu\n", \ 371 TAM3517_year(info), \ 372 TAM3517_week_of_year(info), \ 373 TAM3517_sequence_number(info)); \ 374 printf("Rev: TN%u %u.%u\n", \ 375 TAM3517_revision_tn(info), \ 376 TAM3517_revision_major(info), \ 377 TAM3517_revision_fixed(info)); \ 378 } while (0) 379 380 #endif 381 382 #endif /* __TAM3517_H */ 383