1 /* 2 * Copyright (C) 2011 3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4 * 5 * Copyright (C) 2009 TechNexion Ltd. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __TAM3517_H 11 #define __TAM3517_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 17 #define CONFIG_SYS_TEXT_BASE 0x80008000 18 19 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 20 21 #include <asm/arch/cpu.h> /* get chip and board defs */ 22 #include <asm/arch/omap.h> 23 24 /* Clock Defines */ 25 #define V_OSCK 26000000 /* Clock output from T2 */ 26 #define V_SCLK (V_OSCK >> 1) 27 28 #define CONFIG_MISC_INIT_R 29 30 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 31 #define CONFIG_SETUP_MEMORY_TAGS 32 #define CONFIG_INITRD_TAG 33 #define CONFIG_REVISION_TAG 34 35 /* 36 * Size of malloc() pool 37 */ 38 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 39 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 40 2 * 1024 * 1024) 41 /* 42 * DDR related 43 */ 44 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 45 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 46 47 /* 48 * Hardware drivers 49 */ 50 51 /* 52 * NS16550 Configuration 53 */ 54 #define CONFIG_SYS_NS16550_SERIAL 55 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 56 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 57 58 /* 59 * select serial console configuration 60 */ 61 #define CONFIG_CONS_INDEX 1 62 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 63 #define CONFIG_SERIAL1 /* UART1 */ 64 65 /* allow to overwrite serial and ethaddr */ 66 #define CONFIG_ENV_OVERWRITE 67 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 68 115200} 69 /* EHCI */ 70 #define CONFIG_OMAP3_GPIO_5 71 #define CONFIG_USB_EHCI 72 #define CONFIG_USB_EHCI_OMAP 73 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 74 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 75 76 /* commands to include */ 77 #define CONFIG_CMD_NAND /* NAND support */ 78 #define CONFIG_CMD_EEPROM 79 80 #define CONFIG_SYS_I2C 81 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 82 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 83 #define CONFIG_SYS_I2C_OMAP34XX 84 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 85 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 86 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 87 88 /* 89 * Board NAND Info. 90 */ 91 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 92 /* to access */ 93 /* nand at CS0 */ 94 95 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 96 /* NAND devices */ 97 98 #define CONFIG_AUTO_COMPLETE 99 100 /* 101 * Miscellaneous configurable options 102 */ 103 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 104 #define CONFIG_CMDLINE_EDITING 105 #define CONFIG_AUTO_COMPLETE 106 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 107 108 /* Print Buffer Size */ 109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 110 sizeof(CONFIG_SYS_PROMPT) + 16) 111 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 112 /* args */ 113 /* Boot Argument Buffer Size */ 114 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 115 /* memtest works on */ 116 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 117 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 118 0x01F00000) /* 31MB */ 119 120 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 121 /* address */ 122 123 /* 124 * AM3517 has 12 GP timers, they can be driven by the system clock 125 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 126 * This rate is divided by a local divisor. 127 */ 128 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 129 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 130 131 /* 132 * Physical Memory Map 133 */ 134 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 135 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 136 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 137 138 /* 139 * FLASH and environment organization 140 */ 141 142 /* **** PISMO SUPPORT *** */ 143 #define CONFIG_NAND 144 #define CONFIG_NAND_OMAP_GPMC 145 #define CONFIG_ENV_IS_IN_NAND 146 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 147 148 /* Redundant Environment */ 149 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 150 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 151 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 152 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 153 2 * CONFIG_SYS_ENV_SECT_SIZE) 154 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 155 156 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 157 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 158 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 159 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 160 CONFIG_SYS_INIT_RAM_SIZE - \ 161 GENERATED_GBL_DATA_SIZE) 162 163 /* 164 * ethernet support, EMAC 165 * 166 */ 167 #define CONFIG_DRIVER_TI_EMAC 168 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 169 #define CONFIG_MII 170 #define CONFIG_BOOTP_DNS 171 #define CONFIG_BOOTP_DNS2 172 #define CONFIG_BOOTP_SEND_HOSTNAME 173 #define CONFIG_NET_RETRY_COUNT 10 174 175 /* Defines for SPL */ 176 #define CONFIG_SPL_FRAMEWORK 177 #define CONFIG_SPL_BOARD_INIT 178 #define CONFIG_SPL_CONSOLE 179 #define CONFIG_SPL_NAND_SIMPLE 180 #define CONFIG_SPL_NAND_SOFTECC 181 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 182 183 #define CONFIG_SPL_NAND_BASE 184 #define CONFIG_SPL_NAND_DRIVERS 185 #define CONFIG_SPL_NAND_ECC 186 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 187 188 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 189 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 190 CONFIG_SPL_TEXT_BASE) 191 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 192 193 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 194 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 195 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 196 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 197 198 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 199 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 200 201 /* FAT */ 202 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 203 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 204 205 /* RAW SD card / eMMC */ 206 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ 207 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ 208 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ 209 210 /* NAND boot config */ 211 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 212 #define CONFIG_SYS_NAND_PAGE_COUNT 64 213 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 214 #define CONFIG_SYS_NAND_OOBSIZE 64 215 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 216 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 217 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 218 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 219 48, 49, 50, 51, 52, 53, 54, 55,\ 220 56, 57, 58, 59, 60, 61, 62, 63} 221 #define CONFIG_SYS_NAND_ECCSIZE 256 222 #define CONFIG_SYS_NAND_ECCBYTES 3 223 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 224 #define CONFIG_NAND_OMAP_GPMC_PREFETCH 225 226 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 227 228 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 229 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 230 231 #define CONFIG_CMD_UBIFS 232 #define CONFIG_RBTREE 233 #define CONFIG_LZO 234 #define CONFIG_MTD_PARTITIONS 235 #define CONFIG_MTD_DEVICE 236 #define CONFIG_CMD_MTDPARTS 237 238 /* Setup MTD for NAND on the SOM */ 239 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 240 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 241 "1m(u-boot),256k(env1)," \ 242 "256k(env2),6m(kernel),-(rootfs)" 243 244 #define CONFIG_TAM3517_SETTINGS \ 245 "netdev=eth0\0" \ 246 "nandargs=setenv bootargs root=${nandroot} " \ 247 "rootfstype=${nandrootfstype}\0" \ 248 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 249 "nfsroot=${serverip}:${rootpath}\0" \ 250 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 251 "addip_sta=setenv bootargs ${bootargs} " \ 252 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 253 ":${hostname}:${netdev}:off panic=1\0" \ 254 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 255 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 256 "else run addip_sta;fi\0" \ 257 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 258 "addtty=setenv bootargs ${bootargs}" \ 259 " console=ttyO0,${baudrate}\0" \ 260 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 261 "loadaddr=82000000\0" \ 262 "kernel_addr_r=82000000\0" \ 263 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 264 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 265 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 266 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 267 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 268 "bootm ${kernel_addr}\0" \ 269 "nandboot=run nandargs addip addtty addmtd addmisc;" \ 270 "nand read ${kernel_addr_r} kernel\0" \ 271 "bootm ${kernel_addr_r}\0" \ 272 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 273 "run nfsargs addip addtty addmtd addmisc;" \ 274 "bootm ${kernel_addr_r}\0" \ 275 "net_self=if run net_self_load;then " \ 276 "run ramargs addip addtty addmtd addmisc;" \ 277 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 278 "else echo Images not loades;fi\0" \ 279 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 280 "load=tftp ${loadaddr} ${u-boot}\0" \ 281 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 282 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 283 "uboot_addr=0x80000\0" \ 284 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 285 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 286 "updatemlo=nandecc hw;nand erase 0 20000;" \ 287 "nand write ${loadaddr} 0 20000\0" \ 288 "upd=if run load;then echo Updating u-boot;if run update;" \ 289 "then echo U-Boot updated;" \ 290 "else echo Error updating u-boot !;" \ 291 "echo Board without bootloader !!;" \ 292 "fi;" \ 293 "else echo U-Boot not downloaded..exiting;fi\0" \ 294 295 /* 296 * this is common code for all TAM3517 boards. 297 * MAC address is stored from manufacturer in 298 * I2C EEPROM 299 */ 300 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 301 /* 302 * The I2C EEPROM on the TAM3517 contains 303 * mac address and production data 304 */ 305 struct tam3517_module_info { 306 char customer[48]; 307 char product[48]; 308 309 /* 310 * bit 0~47 : sequence number 311 * bit 48~55 : week of year, from 0. 312 * bit 56~63 : year 313 */ 314 unsigned long long sequence_number; 315 316 /* 317 * bit 0~7 : revision fixed 318 * bit 8~15 : revision major 319 * bit 16~31 : TNxxx 320 */ 321 unsigned int revision; 322 unsigned char eth_addr[4][8]; 323 unsigned char _rev[100]; 324 }; 325 326 #define TAM3517_READ_EEPROM(info, ret) \ 327 do { \ 328 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 329 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 330 (void *)info, sizeof(*info))) \ 331 ret = 1; \ 332 else \ 333 ret = 0; \ 334 } while (0) 335 336 #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 337 do { \ 338 char buf[80], ethname[20]; \ 339 int i; \ 340 memset(buf, 0, sizeof(buf)); \ 341 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 342 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 343 (info)->eth_addr[i][5], \ 344 (info)->eth_addr[i][4], \ 345 (info)->eth_addr[i][3], \ 346 (info)->eth_addr[i][2], \ 347 (info)->eth_addr[i][1], \ 348 (info)->eth_addr[i][0]); \ 349 \ 350 if (i) \ 351 sprintf(ethname, "eth%daddr", i); \ 352 else \ 353 strcpy(ethname, "ethaddr"); \ 354 printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 355 setenv(ethname, buf); \ 356 } \ 357 } while (0) 358 359 /* The following macros are taken from Technexion's documentation */ 360 #define TAM3517_sequence_number(info) \ 361 ((info)->sequence_number % 0x1000000000000LL) 362 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 363 #define TAM3517_year(info) ((info)->sequence_number >> 56) 364 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 365 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 366 #define TAM3517_revision_tn(info) ((info)->revision >> 16) 367 368 #define TAM3517_PRINT_SOM_INFO(info) \ 369 do { \ 370 printf("Vendor:%s\n", (info)->customer); \ 371 printf("SOM: %s\n", (info)->product); \ 372 printf("SeqNr: %02llu%02llu%012llu\n", \ 373 TAM3517_year(info), \ 374 TAM3517_week_of_year(info), \ 375 TAM3517_sequence_number(info)); \ 376 printf("Rev: TN%u %u.%u\n", \ 377 TAM3517_revision_tn(info), \ 378 TAM3517_revision_major(info), \ 379 TAM3517_revision_fixed(info)); \ 380 } while (0) 381 382 #endif 383 384 #endif /* __TAM3517_H */ 385