1*f9c6fac4SStefano Babic /* 2*f9c6fac4SStefano Babic * Copyright (C) 2011 3*f9c6fac4SStefano Babic * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4*f9c6fac4SStefano Babic * 5*f9c6fac4SStefano Babic * Copyright (C) 2009 TechNexion Ltd. 6*f9c6fac4SStefano Babic * 7*f9c6fac4SStefano Babic * This program is free software; you can redistribute it and/or modify 8*f9c6fac4SStefano Babic * it under the terms of the GNU General Public License as published by 9*f9c6fac4SStefano Babic * the Free Software Foundation; either version 2 of the License, or 10*f9c6fac4SStefano Babic * (at your option) any later version. 11*f9c6fac4SStefano Babic * 12*f9c6fac4SStefano Babic * This program is distributed in the hope that it will be useful, 13*f9c6fac4SStefano Babic * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*f9c6fac4SStefano Babic * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*f9c6fac4SStefano Babic * GNU General Public License for more details. 16*f9c6fac4SStefano Babic * 17*f9c6fac4SStefano Babic * You should have received a copy of the GNU General Public License 18*f9c6fac4SStefano Babic * along with this program; if not, write to the Free Software 19*f9c6fac4SStefano Babic * Foundation, Inc. 20*f9c6fac4SStefano Babic */ 21*f9c6fac4SStefano Babic 22*f9c6fac4SStefano Babic #ifndef __TAM3517_H 23*f9c6fac4SStefano Babic #define __TAM3517_H 24*f9c6fac4SStefano Babic 25*f9c6fac4SStefano Babic /* 26*f9c6fac4SStefano Babic * High Level Configuration Options 27*f9c6fac4SStefano Babic */ 28*f9c6fac4SStefano Babic #define CONFIG_OMAP /* in a TI OMAP core */ 29*f9c6fac4SStefano Babic #define CONFIG_OMAP34XX /* which is a 34XX */ 30*f9c6fac4SStefano Babic 31*f9c6fac4SStefano Babic #define CONFIG_SYS_TEXT_BASE 0x80008000 32*f9c6fac4SStefano Babic 33*f9c6fac4SStefano Babic #define CONFIG_SYS_CACHELINE_SIZE 64 34*f9c6fac4SStefano Babic 35*f9c6fac4SStefano Babic #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 36*f9c6fac4SStefano Babic 37*f9c6fac4SStefano Babic #include <asm/arch/cpu.h> /* get chip and board defs */ 38*f9c6fac4SStefano Babic #include <asm/arch/omap3.h> 39*f9c6fac4SStefano Babic 40*f9c6fac4SStefano Babic /* 41*f9c6fac4SStefano Babic * Display CPU and Board information 42*f9c6fac4SStefano Babic */ 43*f9c6fac4SStefano Babic #define CONFIG_DISPLAY_CPUINFO 44*f9c6fac4SStefano Babic #define CONFIG_DISPLAY_BOARDINFO 45*f9c6fac4SStefano Babic 46*f9c6fac4SStefano Babic /* Clock Defines */ 47*f9c6fac4SStefano Babic #define V_OSCK 26000000 /* Clock output from T2 */ 48*f9c6fac4SStefano Babic #define V_SCLK (V_OSCK >> 1) 49*f9c6fac4SStefano Babic 50*f9c6fac4SStefano Babic #undef CONFIG_USE_IRQ /* no support for IRQs */ 51*f9c6fac4SStefano Babic #define CONFIG_MISC_INIT_R 52*f9c6fac4SStefano Babic 53*f9c6fac4SStefano Babic #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 54*f9c6fac4SStefano Babic #define CONFIG_SETUP_MEMORY_TAGS 55*f9c6fac4SStefano Babic #define CONFIG_INITRD_TAG 56*f9c6fac4SStefano Babic #define CONFIG_REVISION_TAG 57*f9c6fac4SStefano Babic 58*f9c6fac4SStefano Babic /* 59*f9c6fac4SStefano Babic * Size of malloc() pool 60*f9c6fac4SStefano Babic */ 61*f9c6fac4SStefano Babic #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 62*f9c6fac4SStefano Babic #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 63*f9c6fac4SStefano Babic 2 * 1024 * 1024) 64*f9c6fac4SStefano Babic /* 65*f9c6fac4SStefano Babic * DDR related 66*f9c6fac4SStefano Babic */ 67*f9c6fac4SStefano Babic #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 68*f9c6fac4SStefano Babic #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 69*f9c6fac4SStefano Babic 70*f9c6fac4SStefano Babic /* 71*f9c6fac4SStefano Babic * Hardware drivers 72*f9c6fac4SStefano Babic */ 73*f9c6fac4SStefano Babic 74*f9c6fac4SStefano Babic /* 75*f9c6fac4SStefano Babic * NS16550 Configuration 76*f9c6fac4SStefano Babic */ 77*f9c6fac4SStefano Babic #define CONFIG_SYS_NS16550 78*f9c6fac4SStefano Babic #define CONFIG_SYS_NS16550_SERIAL 79*f9c6fac4SStefano Babic #define CONFIG_SYS_NS16550_REG_SIZE (-4) 80*f9c6fac4SStefano Babic #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 81*f9c6fac4SStefano Babic 82*f9c6fac4SStefano Babic /* 83*f9c6fac4SStefano Babic * select serial console configuration 84*f9c6fac4SStefano Babic */ 85*f9c6fac4SStefano Babic #define CONFIG_CONS_INDEX 1 86*f9c6fac4SStefano Babic #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 87*f9c6fac4SStefano Babic #define CONFIG_SERIAL1 /* UART1 */ 88*f9c6fac4SStefano Babic 89*f9c6fac4SStefano Babic /* allow to overwrite serial and ethaddr */ 90*f9c6fac4SStefano Babic #define CONFIG_ENV_OVERWRITE 91*f9c6fac4SStefano Babic #define CONFIG_BAUDRATE 115200 92*f9c6fac4SStefano Babic #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 93*f9c6fac4SStefano Babic 115200} 94*f9c6fac4SStefano Babic #define CONFIG_MMC 95*f9c6fac4SStefano Babic #define CONFIG_OMAP_HSMMC 96*f9c6fac4SStefano Babic #define CONFIG_GENERIC_MMC 97*f9c6fac4SStefano Babic #define CONFIG_DOS_PARTITION 98*f9c6fac4SStefano Babic 99*f9c6fac4SStefano Babic /* EHCI */ 100*f9c6fac4SStefano Babic #define CONFIG_OMAP3_GPIO_5 101*f9c6fac4SStefano Babic #define CONFIG_USB_EHCI 102*f9c6fac4SStefano Babic #define CONFIG_USB_EHCI_OMAP 103*f9c6fac4SStefano Babic #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 104*f9c6fac4SStefano Babic #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 105*f9c6fac4SStefano Babic #define CONFIG_USB_STORAGE 106*f9c6fac4SStefano Babic 107*f9c6fac4SStefano Babic /* #define CONFIG_EHCI_DCACHE */ 108*f9c6fac4SStefano Babic 109*f9c6fac4SStefano Babic /* commands to include */ 110*f9c6fac4SStefano Babic #include <config_cmd_default.h> 111*f9c6fac4SStefano Babic 112*f9c6fac4SStefano Babic #define CONFIG_CMD_CACHE 113*f9c6fac4SStefano Babic #define CONFIG_CMD_DHCP 114*f9c6fac4SStefano Babic #define CONFIG_CMD_EXT2 /* EXT2 Support */ 115*f9c6fac4SStefano Babic #define CONFIG_CMD_FAT /* FAT support */ 116*f9c6fac4SStefano Babic #define CONFIG_CMD_GPIO 117*f9c6fac4SStefano Babic #define CONFIG_CMD_I2C /* I2C serial bus support */ 118*f9c6fac4SStefano Babic #define CONFIG_CMD_MII 119*f9c6fac4SStefano Babic #define CONFIG_CMD_MMC /* MMC support */ 120*f9c6fac4SStefano Babic #define CONFIG_CMD_NET 121*f9c6fac4SStefano Babic #define CONFIG_CMD_NFS 122*f9c6fac4SStefano Babic #define CONFIG_CMD_NAND /* NAND support */ 123*f9c6fac4SStefano Babic #define CONFIG_CMD_PING 124*f9c6fac4SStefano Babic #define CONFIG_CMD_USB 125*f9c6fac4SStefano Babic 126*f9c6fac4SStefano Babic #undef CONFIG_CMD_FLASH /* only NAND on the SOM */ 127*f9c6fac4SStefano Babic #undef CONFIG_CMD_IMLS 128*f9c6fac4SStefano Babic 129*f9c6fac4SStefano Babic #define CONFIG_SYS_NO_FLASH 130*f9c6fac4SStefano Babic #define CONFIG_HARD_I2C 131*f9c6fac4SStefano Babic #define CONFIG_SYS_I2C_SPEED 400000 132*f9c6fac4SStefano Babic #define CONFIG_SYS_I2C_SLAVE 1 133*f9c6fac4SStefano Babic #define CONFIG_SYS_I2C_BUS 0 134*f9c6fac4SStefano Babic #define CONFIG_SYS_I2C_BUS_SELECT 1 135*f9c6fac4SStefano Babic #define CONFIG_DRIVER_OMAP34XX_I2C 136*f9c6fac4SStefano Babic 137*f9c6fac4SStefano Babic 138*f9c6fac4SStefano Babic /* 139*f9c6fac4SStefano Babic * Board NAND Info. 140*f9c6fac4SStefano Babic */ 141*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 142*f9c6fac4SStefano Babic /* to access */ 143*f9c6fac4SStefano Babic /* nand at CS0 */ 144*f9c6fac4SStefano Babic 145*f9c6fac4SStefano Babic #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 146*f9c6fac4SStefano Babic /* NAND devices */ 147*f9c6fac4SStefano Babic #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 148*f9c6fac4SStefano Babic 149*f9c6fac4SStefano Babic #define CONFIG_AUTO_COMPLETE 150*f9c6fac4SStefano Babic 151*f9c6fac4SStefano Babic /* 152*f9c6fac4SStefano Babic * Miscellaneous configurable options 153*f9c6fac4SStefano Babic */ 154*f9c6fac4SStefano Babic #define CONFIG_SYS_LONGHELP /* undef to save memory */ 155*f9c6fac4SStefano Babic #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 156*f9c6fac4SStefano Babic #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 157*f9c6fac4SStefano Babic #define CONFIG_CMDLINE_EDITING 158*f9c6fac4SStefano Babic #define CONFIG_AUTO_COMPLETE 159*f9c6fac4SStefano Babic #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 160*f9c6fac4SStefano Babic 161*f9c6fac4SStefano Babic /* Print Buffer Size */ 162*f9c6fac4SStefano Babic #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 163*f9c6fac4SStefano Babic sizeof(CONFIG_SYS_PROMPT) + 16) 164*f9c6fac4SStefano Babic #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 165*f9c6fac4SStefano Babic /* args */ 166*f9c6fac4SStefano Babic /* Boot Argument Buffer Size */ 167*f9c6fac4SStefano Babic #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 168*f9c6fac4SStefano Babic /* memtest works on */ 169*f9c6fac4SStefano Babic #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 170*f9c6fac4SStefano Babic #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 171*f9c6fac4SStefano Babic 0x01F00000) /* 31MB */ 172*f9c6fac4SStefano Babic 173*f9c6fac4SStefano Babic #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 174*f9c6fac4SStefano Babic /* address */ 175*f9c6fac4SStefano Babic 176*f9c6fac4SStefano Babic /* 177*f9c6fac4SStefano Babic * AM3517 has 12 GP timers, they can be driven by the system clock 178*f9c6fac4SStefano Babic * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 179*f9c6fac4SStefano Babic * This rate is divided by a local divisor. 180*f9c6fac4SStefano Babic */ 181*f9c6fac4SStefano Babic #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 182*f9c6fac4SStefano Babic #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 183*f9c6fac4SStefano Babic #define CONFIG_SYS_HZ 1000 184*f9c6fac4SStefano Babic 185*f9c6fac4SStefano Babic /* 186*f9c6fac4SStefano Babic * Stack sizes 187*f9c6fac4SStefano Babic * The stack sizes are set up in start.S using the settings below 188*f9c6fac4SStefano Babic */ 189*f9c6fac4SStefano Babic #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 190*f9c6fac4SStefano Babic 191*f9c6fac4SStefano Babic /* 192*f9c6fac4SStefano Babic * Physical Memory Map 193*f9c6fac4SStefano Babic */ 194*f9c6fac4SStefano Babic #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 195*f9c6fac4SStefano Babic #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 196*f9c6fac4SStefano Babic #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 197*f9c6fac4SStefano Babic #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 198*f9c6fac4SStefano Babic 199*f9c6fac4SStefano Babic /* 200*f9c6fac4SStefano Babic * FLASH and environment organization 201*f9c6fac4SStefano Babic */ 202*f9c6fac4SStefano Babic 203*f9c6fac4SStefano Babic /* **** PISMO SUPPORT *** */ 204*f9c6fac4SStefano Babic 205*f9c6fac4SStefano Babic /* Configure the PISMO */ 206*f9c6fac4SStefano Babic #define PISMO1_NAND_SIZE GPMC_SIZE_128M 207*f9c6fac4SStefano Babic 208*f9c6fac4SStefano Babic #define CONFIG_NAND_OMAP_GPMC 209*f9c6fac4SStefano Babic #define GPMC_NAND_ECC_LP_x16_LAYOUT 210*f9c6fac4SStefano Babic #define CONFIG_ENV_IS_IN_NAND 211*f9c6fac4SStefano Babic #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 212*f9c6fac4SStefano Babic 213*f9c6fac4SStefano Babic /* Redundant Environment */ 214*f9c6fac4SStefano Babic #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 215*f9c6fac4SStefano Babic #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 216*f9c6fac4SStefano Babic #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 217*f9c6fac4SStefano Babic #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 218*f9c6fac4SStefano Babic 2 * CONFIG_SYS_ENV_SECT_SIZE) 219*f9c6fac4SStefano Babic #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 220*f9c6fac4SStefano Babic 221*f9c6fac4SStefano Babic #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 222*f9c6fac4SStefano Babic #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 223*f9c6fac4SStefano Babic #define CONFIG_SYS_INIT_RAM_SIZE 0x800 224*f9c6fac4SStefano Babic #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 225*f9c6fac4SStefano Babic CONFIG_SYS_INIT_RAM_SIZE - \ 226*f9c6fac4SStefano Babic GENERATED_GBL_DATA_SIZE) 227*f9c6fac4SStefano Babic 228*f9c6fac4SStefano Babic /* 229*f9c6fac4SStefano Babic * ethernet support, EMAC 230*f9c6fac4SStefano Babic * 231*f9c6fac4SStefano Babic */ 232*f9c6fac4SStefano Babic #define CONFIG_DRIVER_TI_EMAC 233*f9c6fac4SStefano Babic #define CONFIG_DRIVER_TI_EMAC_USE_RMII 234*f9c6fac4SStefano Babic #define CONFIG_MII 235*f9c6fac4SStefano Babic #define CONFIG_EMAC_MDIO_PHY_NUM 0 236*f9c6fac4SStefano Babic #define CONFIG_BOOTP_DEFAULT 237*f9c6fac4SStefano Babic #define CONFIG_BOOTP_DNS 238*f9c6fac4SStefano Babic #define CONFIG_BOOTP_DNS2 239*f9c6fac4SStefano Babic #define CONFIG_BOOTP_SEND_HOSTNAME 240*f9c6fac4SStefano Babic #define CONFIG_NET_RETRY_COUNT 10 241*f9c6fac4SStefano Babic #define CONFIG_NET_MULTI 242*f9c6fac4SStefano Babic 243*f9c6fac4SStefano Babic /* Defines for SPL */ 244*f9c6fac4SStefano Babic #define CONFIG_SPL 245*f9c6fac4SStefano Babic #define CONFIG_SPL_CONSOLE 246*f9c6fac4SStefano Babic #define CONFIG_SPL_NAND_SIMPLE 247*f9c6fac4SStefano Babic #define CONFIG_SPL_NAND_SOFTECC 248*f9c6fac4SStefano Babic #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 249*f9c6fac4SStefano Babic 250*f9c6fac4SStefano Babic #define CONFIG_SPL_LIBCOMMON_SUPPORT 251*f9c6fac4SStefano Babic #define CONFIG_SPL_LIBDISK_SUPPORT 252*f9c6fac4SStefano Babic #define CONFIG_SPL_I2C_SUPPORT 253*f9c6fac4SStefano Babic #define CONFIG_SPL_LIBGENERIC_SUPPORT 254*f9c6fac4SStefano Babic #define CONFIG_SPL_SERIAL_SUPPORT 255*f9c6fac4SStefano Babic #define CONFIG_SPL_POWER_SUPPORT 256*f9c6fac4SStefano Babic #define CONFIG_SPL_NAND_SUPPORT 257*f9c6fac4SStefano Babic #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 258*f9c6fac4SStefano Babic 259*f9c6fac4SStefano Babic #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 260*f9c6fac4SStefano Babic #define CONFIG_SPL_MAX_SIZE (45 << 10) /* 45 K */ 261*f9c6fac4SStefano Babic #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 262*f9c6fac4SStefano Babic 263*f9c6fac4SStefano Babic #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 264*f9c6fac4SStefano Babic #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 265*f9c6fac4SStefano Babic #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 266*f9c6fac4SStefano Babic #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 267*f9c6fac4SStefano Babic 268*f9c6fac4SStefano Babic /* NAND boot config */ 269*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_PAGE_COUNT 64 270*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_PAGE_SIZE 2048 271*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_OOBSIZE 64 272*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 273*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_5_ADDR_CYCLE 274*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 275*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 276*f9c6fac4SStefano Babic 48, 49, 50, 51, 52, 53, 54, 55,\ 277*f9c6fac4SStefano Babic 56, 57, 58, 59, 60, 61, 62, 63} 278*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_ECCSIZE 256 279*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_ECCBYTES 3 280*f9c6fac4SStefano Babic 281*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ 282*f9c6fac4SStefano Babic CONFIG_SYS_NAND_ECCSIZE) 283*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ 284*f9c6fac4SStefano Babic CONFIG_SYS_NAND_ECCSTEPS) 285*f9c6fac4SStefano Babic 286*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 287*f9c6fac4SStefano Babic 288*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 289*f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 290*f9c6fac4SStefano Babic 291*f9c6fac4SStefano Babic #define CONFIG_OF_LIBFDT 292*f9c6fac4SStefano Babic #define CONFIG_FIT 293*f9c6fac4SStefano Babic #define CONFIG_CMD_UBI 294*f9c6fac4SStefano Babic #define CONFIG_CMD_UBIFS 295*f9c6fac4SStefano Babic #define CONFIG_RBTREE 296*f9c6fac4SStefano Babic #define CONFIG_LZO 297*f9c6fac4SStefano Babic #define CONFIG_MTD_PARTITIONS 298*f9c6fac4SStefano Babic #define CONFIG_MTD_DEVICE 299*f9c6fac4SStefano Babic #define CONFIG_CMD_MTDPARTS 300*f9c6fac4SStefano Babic 301*f9c6fac4SStefano Babic /* Setup MTD for NAND on the SOM */ 302*f9c6fac4SStefano Babic #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 303*f9c6fac4SStefano Babic #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 304*f9c6fac4SStefano Babic "512k(u-boot),128k(env1)," \ 305*f9c6fac4SStefano Babic "128k(env2),6m(kernel),-(rootfs)" 306*f9c6fac4SStefano Babic 307*f9c6fac4SStefano Babic #define xstr(s) str(s) 308*f9c6fac4SStefano Babic #define str(s) #s 309*f9c6fac4SStefano Babic 310*f9c6fac4SStefano Babic #define CONFIG_TAM3517_SETTINGS \ 311*f9c6fac4SStefano Babic "netdev=eth0\0" \ 312*f9c6fac4SStefano Babic "nandargs=setenv bootargs root=${nandroot} " \ 313*f9c6fac4SStefano Babic "rootfstype=${nandrootfstype}\0" \ 314*f9c6fac4SStefano Babic "nfsargs=setenv bootargs root=/dev/nfs rw " \ 315*f9c6fac4SStefano Babic "nfsroot=${serverip}:${rootpath}\0" \ 316*f9c6fac4SStefano Babic "ramargs=setenv bootargs root=/dev/ram rw\0" \ 317*f9c6fac4SStefano Babic "addip_sta=setenv bootargs ${bootargs} " \ 318*f9c6fac4SStefano Babic "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 319*f9c6fac4SStefano Babic ":${hostname}:${netdev}:off panic=1\0" \ 320*f9c6fac4SStefano Babic "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 321*f9c6fac4SStefano Babic "addip=if test -n ${ipdyn};then run addip_dyn;" \ 322*f9c6fac4SStefano Babic "else run addip_sta;fi\0" \ 323*f9c6fac4SStefano Babic "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 324*f9c6fac4SStefano Babic "addtty=setenv bootargs ${bootargs}" \ 325*f9c6fac4SStefano Babic " console=ttyO0,${baudrate}\0" \ 326*f9c6fac4SStefano Babic "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 327*f9c6fac4SStefano Babic "loadaddr=82000000\0" \ 328*f9c6fac4SStefano Babic "kernel_addr_r=82000000\0" \ 329*f9c6fac4SStefano Babic "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ 330*f9c6fac4SStefano Babic "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ 331*f9c6fac4SStefano Babic "flash_self=run ramargs addip addtty addmtd addmisc;" \ 332*f9c6fac4SStefano Babic "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 333*f9c6fac4SStefano Babic "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 334*f9c6fac4SStefano Babic "bootm ${kernel_addr}\0" \ 335*f9c6fac4SStefano Babic "nandboot=run nandargs addip addtty addmtd addmisc;" \ 336*f9c6fac4SStefano Babic "nand read ${kernel_addr_r} kernel\0" \ 337*f9c6fac4SStefano Babic "bootm ${kernel_addr_r}\0" \ 338*f9c6fac4SStefano Babic "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 339*f9c6fac4SStefano Babic "run nfsargs addip addtty addmtd addmisc;" \ 340*f9c6fac4SStefano Babic "bootm ${kernel_addr_r}\0" \ 341*f9c6fac4SStefano Babic "net_self=if run net_self_load;then " \ 342*f9c6fac4SStefano Babic "run ramargs addip addtty addmtd addmisc;" \ 343*f9c6fac4SStefano Babic "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 344*f9c6fac4SStefano Babic "else echo Images not loades;fi\0" \ 345*f9c6fac4SStefano Babic "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \ 346*f9c6fac4SStefano Babic "load=tftp ${loadaddr} ${u-boot}\0" \ 347*f9c6fac4SStefano Babic "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 348*f9c6fac4SStefano Babic "mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \ 349*f9c6fac4SStefano Babic "uboot_addr=0x80000\0" \ 350*f9c6fac4SStefano Babic "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 351*f9c6fac4SStefano Babic "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 352*f9c6fac4SStefano Babic "updatemlo=nandecc hw;nand erase 0 20000;" \ 353*f9c6fac4SStefano Babic "nand write ${loadaddr} 0 20000\0" \ 354*f9c6fac4SStefano Babic "upd=if run load;then echo Updating u-boot;if run update;" \ 355*f9c6fac4SStefano Babic "then echo U-Boot updated;" \ 356*f9c6fac4SStefano Babic "else echo Error updating u-boot !;" \ 357*f9c6fac4SStefano Babic "echo Board without bootloader !!;" \ 358*f9c6fac4SStefano Babic "fi;" \ 359*f9c6fac4SStefano Babic "else echo U-Boot not downloaded..exiting;fi\0" \ 360*f9c6fac4SStefano Babic 361*f9c6fac4SStefano Babic #endif /* __TAM3517_H */ 362