1f9c6fac4SStefano Babic /* 2f9c6fac4SStefano Babic * Copyright (C) 2011 3f9c6fac4SStefano Babic * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 4f9c6fac4SStefano Babic * 5f9c6fac4SStefano Babic * Copyright (C) 2009 TechNexion Ltd. 6f9c6fac4SStefano Babic * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8f9c6fac4SStefano Babic */ 9f9c6fac4SStefano Babic 10f9c6fac4SStefano Babic #ifndef __TAM3517_H 11f9c6fac4SStefano Babic #define __TAM3517_H 12f9c6fac4SStefano Babic 13f9c6fac4SStefano Babic /* 14f9c6fac4SStefano Babic * High Level Configuration Options 15f9c6fac4SStefano Babic */ 16f9c6fac4SStefano Babic #define CONFIG_OMAP /* in a TI OMAP core */ 17308252adSMarek Vasut #define CONFIG_OMAP_GPIO 18806d2792SLokesh Vutla #define CONFIG_OMAP_COMMON 19457baf54SJeroen Hofstee #define CONFIG_SYS_GENERIC_BOARD 20c6f90e14SNishanth Menon /* Common ARM Erratas */ 21c6f90e14SNishanth Menon #define CONFIG_ARM_ERRATA_454179 22c6f90e14SNishanth Menon #define CONFIG_ARM_ERRATA_430973 23c6f90e14SNishanth Menon #define CONFIG_ARM_ERRATA_621766 24f9c6fac4SStefano Babic 25f9c6fac4SStefano Babic #define CONFIG_SYS_TEXT_BASE 0x80008000 26f9c6fac4SStefano Babic 27f9c6fac4SStefano Babic #define CONFIG_SYS_CACHELINE_SIZE 64 28f9c6fac4SStefano Babic 29f9c6fac4SStefano Babic #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 30f9c6fac4SStefano Babic 31f9c6fac4SStefano Babic #include <asm/arch/cpu.h> /* get chip and board defs */ 32987ec585SNishanth Menon #include <asm/arch/omap.h> 33f9c6fac4SStefano Babic 34f9c6fac4SStefano Babic /* 35f9c6fac4SStefano Babic * Display CPU and Board information 36f9c6fac4SStefano Babic */ 37f9c6fac4SStefano Babic #define CONFIG_DISPLAY_CPUINFO 38f9c6fac4SStefano Babic #define CONFIG_DISPLAY_BOARDINFO 39f9c6fac4SStefano Babic 40f9c6fac4SStefano Babic /* Clock Defines */ 41f9c6fac4SStefano Babic #define V_OSCK 26000000 /* Clock output from T2 */ 42f9c6fac4SStefano Babic #define V_SCLK (V_OSCK >> 1) 43f9c6fac4SStefano Babic 44f9c6fac4SStefano Babic #define CONFIG_MISC_INIT_R 45f9c6fac4SStefano Babic 46f9c6fac4SStefano Babic #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 47f9c6fac4SStefano Babic #define CONFIG_SETUP_MEMORY_TAGS 48f9c6fac4SStefano Babic #define CONFIG_INITRD_TAG 49f9c6fac4SStefano Babic #define CONFIG_REVISION_TAG 50f9c6fac4SStefano Babic 51f9c6fac4SStefano Babic /* 52f9c6fac4SStefano Babic * Size of malloc() pool 53f9c6fac4SStefano Babic */ 54f9c6fac4SStefano Babic #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 55f9c6fac4SStefano Babic #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ 56f9c6fac4SStefano Babic 2 * 1024 * 1024) 57f9c6fac4SStefano Babic /* 58f9c6fac4SStefano Babic * DDR related 59f9c6fac4SStefano Babic */ 60f9c6fac4SStefano Babic #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ 61f9c6fac4SStefano Babic #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 62f9c6fac4SStefano Babic 63f9c6fac4SStefano Babic /* 64f9c6fac4SStefano Babic * Hardware drivers 65f9c6fac4SStefano Babic */ 66f9c6fac4SStefano Babic 67f9c6fac4SStefano Babic /* 68f9c6fac4SStefano Babic * NS16550 Configuration 69f9c6fac4SStefano Babic */ 70f9c6fac4SStefano Babic #define CONFIG_SYS_NS16550 71f9c6fac4SStefano Babic #define CONFIG_SYS_NS16550_SERIAL 72f9c6fac4SStefano Babic #define CONFIG_SYS_NS16550_REG_SIZE (-4) 73f9c6fac4SStefano Babic #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 74f9c6fac4SStefano Babic 75f9c6fac4SStefano Babic /* 76f9c6fac4SStefano Babic * select serial console configuration 77f9c6fac4SStefano Babic */ 78f9c6fac4SStefano Babic #define CONFIG_CONS_INDEX 1 79f9c6fac4SStefano Babic #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 80f9c6fac4SStefano Babic #define CONFIG_SERIAL1 /* UART1 */ 81f9c6fac4SStefano Babic 82f9c6fac4SStefano Babic /* allow to overwrite serial and ethaddr */ 83f9c6fac4SStefano Babic #define CONFIG_ENV_OVERWRITE 84f9c6fac4SStefano Babic #define CONFIG_BAUDRATE 115200 85f9c6fac4SStefano Babic #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 86f9c6fac4SStefano Babic 115200} 87f9c6fac4SStefano Babic #define CONFIG_MMC 88f9c6fac4SStefano Babic #define CONFIG_OMAP_HSMMC 89f9c6fac4SStefano Babic #define CONFIG_GENERIC_MMC 90f9c6fac4SStefano Babic #define CONFIG_DOS_PARTITION 91f9c6fac4SStefano Babic 92f9c6fac4SStefano Babic /* EHCI */ 93f9c6fac4SStefano Babic #define CONFIG_OMAP3_GPIO_5 94f9c6fac4SStefano Babic #define CONFIG_USB_EHCI 95f9c6fac4SStefano Babic #define CONFIG_USB_EHCI_OMAP 968c589d6fSStefano Babic #define CONFIG_USB_ULPI 978c589d6fSStefano Babic #define CONFIG_USB_ULPI_VIEWPORT_OMAP 98f9c6fac4SStefano Babic #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 99f9c6fac4SStefano Babic #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 100f9c6fac4SStefano Babic #define CONFIG_USB_STORAGE 101f9c6fac4SStefano Babic 102f9c6fac4SStefano Babic /* commands to include */ 103f9c6fac4SStefano Babic #include <config_cmd_default.h> 104f9c6fac4SStefano Babic 105f9c6fac4SStefano Babic #define CONFIG_CMD_CACHE 106f9c6fac4SStefano Babic #define CONFIG_CMD_DHCP 107f9c6fac4SStefano Babic #define CONFIG_CMD_EXT2 /* EXT2 Support */ 108f9c6fac4SStefano Babic #define CONFIG_CMD_FAT /* FAT support */ 109f9c6fac4SStefano Babic #define CONFIG_CMD_GPIO 110f9c6fac4SStefano Babic #define CONFIG_CMD_I2C /* I2C serial bus support */ 111f9c6fac4SStefano Babic #define CONFIG_CMD_MII 112f9c6fac4SStefano Babic #define CONFIG_CMD_MMC /* MMC support */ 113f9c6fac4SStefano Babic #define CONFIG_CMD_NFS 114f9c6fac4SStefano Babic #define CONFIG_CMD_NAND /* NAND support */ 115f9c6fac4SStefano Babic #define CONFIG_CMD_PING 116f9c6fac4SStefano Babic #define CONFIG_CMD_USB 1178103c6f0SStefano Babic #define CONFIG_CMD_EEPROM 118f9c6fac4SStefano Babic 119f9c6fac4SStefano Babic #undef CONFIG_CMD_FLASH /* only NAND on the SOM */ 120f9c6fac4SStefano Babic #undef CONFIG_CMD_IMLS 121f9c6fac4SStefano Babic 122f9c6fac4SStefano Babic #define CONFIG_SYS_NO_FLASH 1236789e84eSHeiko Schocher #define CONFIG_SYS_I2C 1246789e84eSHeiko Schocher #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 1256789e84eSHeiko Schocher #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 1266789e84eSHeiko Schocher #define CONFIG_SYS_I2C_OMAP34XX 1278103c6f0SStefano Babic #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 1288103c6f0SStefano Babic #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 1298103c6f0SStefano Babic #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 130f9c6fac4SStefano Babic 131f9c6fac4SStefano Babic /* 132f9c6fac4SStefano Babic * Board NAND Info. 133f9c6fac4SStefano Babic */ 134f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 135f9c6fac4SStefano Babic /* to access */ 136f9c6fac4SStefano Babic /* nand at CS0 */ 137f9c6fac4SStefano Babic 138f9c6fac4SStefano Babic #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 139f9c6fac4SStefano Babic /* NAND devices */ 140f9c6fac4SStefano Babic 141f9c6fac4SStefano Babic #define CONFIG_AUTO_COMPLETE 142f9c6fac4SStefano Babic 143f9c6fac4SStefano Babic /* 144f9c6fac4SStefano Babic * Miscellaneous configurable options 145f9c6fac4SStefano Babic */ 146f9c6fac4SStefano Babic #define CONFIG_SYS_LONGHELP /* undef to save memory */ 147f9c6fac4SStefano Babic #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 148f9c6fac4SStefano Babic #define CONFIG_CMDLINE_EDITING 149f9c6fac4SStefano Babic #define CONFIG_AUTO_COMPLETE 150f9c6fac4SStefano Babic #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 151f9c6fac4SStefano Babic 152f9c6fac4SStefano Babic /* Print Buffer Size */ 153f9c6fac4SStefano Babic #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 154f9c6fac4SStefano Babic sizeof(CONFIG_SYS_PROMPT) + 16) 155f9c6fac4SStefano Babic #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 156f9c6fac4SStefano Babic /* args */ 157f9c6fac4SStefano Babic /* Boot Argument Buffer Size */ 158f9c6fac4SStefano Babic #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 159f9c6fac4SStefano Babic /* memtest works on */ 160f9c6fac4SStefano Babic #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 161f9c6fac4SStefano Babic #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 162f9c6fac4SStefano Babic 0x01F00000) /* 31MB */ 163f9c6fac4SStefano Babic 164f9c6fac4SStefano Babic #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 165f9c6fac4SStefano Babic /* address */ 166f9c6fac4SStefano Babic 167f9c6fac4SStefano Babic /* 168f9c6fac4SStefano Babic * AM3517 has 12 GP timers, they can be driven by the system clock 169f9c6fac4SStefano Babic * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 170f9c6fac4SStefano Babic * This rate is divided by a local divisor. 171f9c6fac4SStefano Babic */ 172f9c6fac4SStefano Babic #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 173f9c6fac4SStefano Babic #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 174f9c6fac4SStefano Babic 175f9c6fac4SStefano Babic /* 176f9c6fac4SStefano Babic * Physical Memory Map 177f9c6fac4SStefano Babic */ 178f9c6fac4SStefano Babic #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 179f9c6fac4SStefano Babic #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 180f9c6fac4SStefano Babic #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 181f9c6fac4SStefano Babic 182f9c6fac4SStefano Babic /* 183f9c6fac4SStefano Babic * FLASH and environment organization 184f9c6fac4SStefano Babic */ 185f9c6fac4SStefano Babic 186f9c6fac4SStefano Babic /* **** PISMO SUPPORT *** */ 1870970051dSJeroen Hofstee #define CONFIG_NAND 188f9c6fac4SStefano Babic #define CONFIG_NAND_OMAP_GPMC 189f9c6fac4SStefano Babic #define CONFIG_ENV_IS_IN_NAND 190f9c6fac4SStefano Babic #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ 191f9c6fac4SStefano Babic 192f9c6fac4SStefano Babic /* Redundant Environment */ 193f9c6fac4SStefano Babic #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 194f9c6fac4SStefano Babic #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 195f9c6fac4SStefano Babic #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 196f9c6fac4SStefano Babic #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 197f9c6fac4SStefano Babic 2 * CONFIG_SYS_ENV_SECT_SIZE) 198f9c6fac4SStefano Babic #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 199f9c6fac4SStefano Babic 200f9c6fac4SStefano Babic #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 201f9c6fac4SStefano Babic #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 202f9c6fac4SStefano Babic #define CONFIG_SYS_INIT_RAM_SIZE 0x800 203f9c6fac4SStefano Babic #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 204f9c6fac4SStefano Babic CONFIG_SYS_INIT_RAM_SIZE - \ 205f9c6fac4SStefano Babic GENERATED_GBL_DATA_SIZE) 206f9c6fac4SStefano Babic 207f9c6fac4SStefano Babic /* 208f9c6fac4SStefano Babic * ethernet support, EMAC 209f9c6fac4SStefano Babic * 210f9c6fac4SStefano Babic */ 211f9c6fac4SStefano Babic #define CONFIG_DRIVER_TI_EMAC 212f9c6fac4SStefano Babic #define CONFIG_DRIVER_TI_EMAC_USE_RMII 213f9c6fac4SStefano Babic #define CONFIG_MII 214f9c6fac4SStefano Babic #define CONFIG_EMAC_MDIO_PHY_NUM 0 215f9c6fac4SStefano Babic #define CONFIG_BOOTP_DNS 216f9c6fac4SStefano Babic #define CONFIG_BOOTP_DNS2 217f9c6fac4SStefano Babic #define CONFIG_BOOTP_SEND_HOSTNAME 218f9c6fac4SStefano Babic #define CONFIG_NET_RETRY_COUNT 10 219f9c6fac4SStefano Babic 220f9c6fac4SStefano Babic /* Defines for SPL */ 22147f7bcaeSTom Rini #define CONFIG_SPL_FRAMEWORK 222d7cb93b2STom Rini #define CONFIG_SPL_BOARD_INIT 223f9c6fac4SStefano Babic #define CONFIG_SPL_CONSOLE 224f9c6fac4SStefano Babic #define CONFIG_SPL_NAND_SIMPLE 2258ad59c9aSJeroen Hofstee #define CONFIG_SPL_NAND_SOFTECC 226f9c6fac4SStefano Babic #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ 227f9c6fac4SStefano Babic 228f9c6fac4SStefano Babic #define CONFIG_SPL_LIBCOMMON_SUPPORT 229f9c6fac4SStefano Babic #define CONFIG_SPL_LIBDISK_SUPPORT 230f9c6fac4SStefano Babic #define CONFIG_SPL_I2C_SUPPORT 231f9c6fac4SStefano Babic #define CONFIG_SPL_LIBGENERIC_SUPPORT 232f9c6fac4SStefano Babic #define CONFIG_SPL_SERIAL_SUPPORT 23316e41c85SMarek Vasut #define CONFIG_SPL_GPIO_SUPPORT 234f9c6fac4SStefano Babic #define CONFIG_SPL_POWER_SUPPORT 235f9c6fac4SStefano Babic #define CONFIG_SPL_NAND_SUPPORT 2366f2f01b9SScott Wood #define CONFIG_SPL_NAND_BASE 2376f2f01b9SScott Wood #define CONFIG_SPL_NAND_DRIVERS 2386f2f01b9SScott Wood #define CONFIG_SPL_NAND_ECC 239f9c6fac4SStefano Babic #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 240f9c6fac4SStefano Babic 241f9c6fac4SStefano Babic #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 242e0820cccSTom Rini #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 243f9c6fac4SStefano Babic 244f9c6fac4SStefano Babic #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 245f9c6fac4SStefano Babic #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 246f9c6fac4SStefano Babic #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 247f9c6fac4SStefano Babic #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 248f9c6fac4SStefano Babic 249f9c6fac4SStefano Babic /* NAND boot config */ 250b80a6603Spekon gupta #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 251f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_PAGE_COUNT 64 252f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_PAGE_SIZE 2048 253f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_OOBSIZE 64 254f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 255f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_5_ADDR_CYCLE 256f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 257f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 258f9c6fac4SStefano Babic 48, 49, 50, 51, 52, 53, 54, 55,\ 259f9c6fac4SStefano Babic 56, 57, 58, 59, 60, 61, 62, 63} 260f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_ECCSIZE 256 261f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_ECCBYTES 3 2623f719069Spekon gupta #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 263*817aa32bSJeroen Hofstee #define CONFIG_NAND_OMAP_GPMC_PREFETCH 264f9c6fac4SStefano Babic 265f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 266f9c6fac4SStefano Babic 267f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 268f9c6fac4SStefano Babic #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 269f9c6fac4SStefano Babic 270f9c6fac4SStefano Babic #define CONFIG_OF_LIBFDT 271f9c6fac4SStefano Babic #define CONFIG_FIT 272f9c6fac4SStefano Babic #define CONFIG_CMD_UBI 273f9c6fac4SStefano Babic #define CONFIG_CMD_UBIFS 274f9c6fac4SStefano Babic #define CONFIG_RBTREE 275f9c6fac4SStefano Babic #define CONFIG_LZO 276f9c6fac4SStefano Babic #define CONFIG_MTD_PARTITIONS 277f9c6fac4SStefano Babic #define CONFIG_MTD_DEVICE 278f9c6fac4SStefano Babic #define CONFIG_CMD_MTDPARTS 279f9c6fac4SStefano Babic 280f9c6fac4SStefano Babic /* Setup MTD for NAND on the SOM */ 281f9c6fac4SStefano Babic #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 282f9c6fac4SStefano Babic #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ 2831fdabeddSStefano Babic "1m(u-boot),256k(env1)," \ 2841fdabeddSStefano Babic "256k(env2),6m(kernel),-(rootfs)" 285f9c6fac4SStefano Babic 286f9c6fac4SStefano Babic #define CONFIG_TAM3517_SETTINGS \ 287f9c6fac4SStefano Babic "netdev=eth0\0" \ 288f9c6fac4SStefano Babic "nandargs=setenv bootargs root=${nandroot} " \ 289f9c6fac4SStefano Babic "rootfstype=${nandrootfstype}\0" \ 290f9c6fac4SStefano Babic "nfsargs=setenv bootargs root=/dev/nfs rw " \ 291f9c6fac4SStefano Babic "nfsroot=${serverip}:${rootpath}\0" \ 292f9c6fac4SStefano Babic "ramargs=setenv bootargs root=/dev/ram rw\0" \ 293f9c6fac4SStefano Babic "addip_sta=setenv bootargs ${bootargs} " \ 294f9c6fac4SStefano Babic "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 295f9c6fac4SStefano Babic ":${hostname}:${netdev}:off panic=1\0" \ 296f9c6fac4SStefano Babic "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 297f9c6fac4SStefano Babic "addip=if test -n ${ipdyn};then run addip_dyn;" \ 298f9c6fac4SStefano Babic "else run addip_sta;fi\0" \ 299f9c6fac4SStefano Babic "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 300f9c6fac4SStefano Babic "addtty=setenv bootargs ${bootargs}" \ 301f9c6fac4SStefano Babic " console=ttyO0,${baudrate}\0" \ 302f9c6fac4SStefano Babic "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 303f9c6fac4SStefano Babic "loadaddr=82000000\0" \ 304f9c6fac4SStefano Babic "kernel_addr_r=82000000\0" \ 30593ea89f0SMarek Vasut "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 30693ea89f0SMarek Vasut "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 307f9c6fac4SStefano Babic "flash_self=run ramargs addip addtty addmtd addmisc;" \ 308f9c6fac4SStefano Babic "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 309f9c6fac4SStefano Babic "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 310f9c6fac4SStefano Babic "bootm ${kernel_addr}\0" \ 311f9c6fac4SStefano Babic "nandboot=run nandargs addip addtty addmtd addmisc;" \ 312f9c6fac4SStefano Babic "nand read ${kernel_addr_r} kernel\0" \ 313f9c6fac4SStefano Babic "bootm ${kernel_addr_r}\0" \ 314f9c6fac4SStefano Babic "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 315f9c6fac4SStefano Babic "run nfsargs addip addtty addmtd addmisc;" \ 316f9c6fac4SStefano Babic "bootm ${kernel_addr_r}\0" \ 317f9c6fac4SStefano Babic "net_self=if run net_self_load;then " \ 318f9c6fac4SStefano Babic "run ramargs addip addtty addmtd addmisc;" \ 319f9c6fac4SStefano Babic "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ 320f9c6fac4SStefano Babic "else echo Images not loades;fi\0" \ 32193ea89f0SMarek Vasut "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ 322f9c6fac4SStefano Babic "load=tftp ${loadaddr} ${u-boot}\0" \ 323f9c6fac4SStefano Babic "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 32493ea89f0SMarek Vasut "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ 325f9c6fac4SStefano Babic "uboot_addr=0x80000\0" \ 326f9c6fac4SStefano Babic "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 327f9c6fac4SStefano Babic "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 328f9c6fac4SStefano Babic "updatemlo=nandecc hw;nand erase 0 20000;" \ 329f9c6fac4SStefano Babic "nand write ${loadaddr} 0 20000\0" \ 330f9c6fac4SStefano Babic "upd=if run load;then echo Updating u-boot;if run update;" \ 331f9c6fac4SStefano Babic "then echo U-Boot updated;" \ 332f9c6fac4SStefano Babic "else echo Error updating u-boot !;" \ 333f9c6fac4SStefano Babic "echo Board without bootloader !!;" \ 334f9c6fac4SStefano Babic "fi;" \ 335f9c6fac4SStefano Babic "else echo U-Boot not downloaded..exiting;fi\0" \ 336f9c6fac4SStefano Babic 3378103c6f0SStefano Babic 3388103c6f0SStefano Babic /* 3398103c6f0SStefano Babic * this is common code for all TAM3517 boards. 3408103c6f0SStefano Babic * MAC address is stored from manufacturer in 3418103c6f0SStefano Babic * I2C EEPROM 3428103c6f0SStefano Babic */ 3438103c6f0SStefano Babic #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 3448103c6f0SStefano Babic /* 3458103c6f0SStefano Babic * The I2C EEPROM on the TAM3517 contains 3468103c6f0SStefano Babic * mac address and production data 3478103c6f0SStefano Babic */ 3488103c6f0SStefano Babic struct tam3517_module_info { 3498103c6f0SStefano Babic char customer[48]; 3508103c6f0SStefano Babic char product[48]; 3518103c6f0SStefano Babic 3528103c6f0SStefano Babic /* 3538103c6f0SStefano Babic * bit 0~47 : sequence number 3548103c6f0SStefano Babic * bit 48~55 : week of year, from 0. 3558103c6f0SStefano Babic * bit 56~63 : year 3568103c6f0SStefano Babic */ 3578103c6f0SStefano Babic unsigned long long sequence_number; 3588103c6f0SStefano Babic 3598103c6f0SStefano Babic /* 3608103c6f0SStefano Babic * bit 0~7 : revision fixed 3618103c6f0SStefano Babic * bit 8~15 : revision major 3628103c6f0SStefano Babic * bit 16~31 : TNxxx 3638103c6f0SStefano Babic */ 3648103c6f0SStefano Babic unsigned int revision; 3658103c6f0SStefano Babic unsigned char eth_addr[4][8]; 3668103c6f0SStefano Babic unsigned char _rev[100]; 3678103c6f0SStefano Babic }; 3688103c6f0SStefano Babic 36931f5b651SStefano Babic #define TAM3517_READ_EEPROM(info, ret) \ 3708103c6f0SStefano Babic do { \ 3716789e84eSHeiko Schocher i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ 3728103c6f0SStefano Babic if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ 37331f5b651SStefano Babic (void *)info, sizeof(*info))) \ 37431f5b651SStefano Babic ret = 1; \ 37531f5b651SStefano Babic else \ 37631f5b651SStefano Babic ret = 0; \ 37731f5b651SStefano Babic } while (0) 37831f5b651SStefano Babic 37931f5b651SStefano Babic #define TAM3517_READ_MAC_FROM_EEPROM(info) \ 38031f5b651SStefano Babic do { \ 38131f5b651SStefano Babic char buf[80], ethname[20]; \ 38231f5b651SStefano Babic int i; \ 3838103c6f0SStefano Babic memset(buf, 0, sizeof(buf)); \ 38431f5b651SStefano Babic for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ 3858103c6f0SStefano Babic sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ 38631f5b651SStefano Babic (info)->eth_addr[i][5], \ 38731f5b651SStefano Babic (info)->eth_addr[i][4], \ 38831f5b651SStefano Babic (info)->eth_addr[i][3], \ 38931f5b651SStefano Babic (info)->eth_addr[i][2], \ 39031f5b651SStefano Babic (info)->eth_addr[i][1], \ 39131f5b651SStefano Babic (info)->eth_addr[i][0]); \ 3928103c6f0SStefano Babic \ 3938103c6f0SStefano Babic if (i) \ 3948103c6f0SStefano Babic sprintf(ethname, "eth%daddr", i); \ 3958103c6f0SStefano Babic else \ 3968103c6f0SStefano Babic sprintf(ethname, "ethaddr"); \ 3978103c6f0SStefano Babic printf("Setting %s from EEPROM with %s\n", ethname, buf);\ 3988103c6f0SStefano Babic setenv(ethname, buf); \ 3998103c6f0SStefano Babic } \ 4008103c6f0SStefano Babic } while (0) 40131f5b651SStefano Babic 40231f5b651SStefano Babic /* The following macros are taken from Technexion's documentation */ 40331f5b651SStefano Babic #define TAM3517_sequence_number(info) \ 40431f5b651SStefano Babic ((info)->sequence_number % 0x1000000000000LL) 40531f5b651SStefano Babic #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) 40631f5b651SStefano Babic #define TAM3517_year(info) ((info)->sequence_number >> 56) 40731f5b651SStefano Babic #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) 40831f5b651SStefano Babic #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) 40931f5b651SStefano Babic #define TAM3517_revision_tn(info) ((info)->revision >> 16) 41031f5b651SStefano Babic 41131f5b651SStefano Babic #define TAM3517_PRINT_SOM_INFO(info) \ 41231f5b651SStefano Babic do { \ 41331f5b651SStefano Babic printf("Vendor:%s\n", (info)->customer); \ 41431f5b651SStefano Babic printf("SOM: %s\n", (info)->product); \ 41531f5b651SStefano Babic printf("SeqNr: %02llu%02llu%012llu\n", \ 41631f5b651SStefano Babic TAM3517_year(info), \ 41731f5b651SStefano Babic TAM3517_week_of_year(info), \ 41831f5b651SStefano Babic TAM3517_sequence_number(info)); \ 41931f5b651SStefano Babic printf("Rev: TN%u %u.%u\n", \ 42031f5b651SStefano Babic TAM3517_revision_tn(info), \ 42131f5b651SStefano Babic TAM3517_revision_major(info), \ 42231f5b651SStefano Babic TAM3517_revision_fixed(info)); \ 42331f5b651SStefano Babic } while (0) 42431f5b651SStefano Babic 4258103c6f0SStefano Babic #endif 4268103c6f0SStefano Babic 427f9c6fac4SStefano Babic #endif /* __TAM3517_H */ 428