1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #ifdef CONFIG_RAMBOOT_PBL 14 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 15 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 16 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg 17 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg 18 #endif 19 20 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 21 /* Set 1M boot space */ 22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 23 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 24 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_NO_FLASH 27 #endif 28 29 #define CONFIG_CMD_REGINFO 30 31 /* High Level Configuration Options */ 32 #define CONFIG_BOOKE 33 #define CONFIG_E500 /* BOOKE e500 family */ 34 #define CONFIG_E500MC /* BOOKE e500mc family */ 35 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 36 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 37 #define CONFIG_MP /* support multiple processors */ 38 39 #ifndef CONFIG_SYS_TEXT_BASE 40 #define CONFIG_SYS_TEXT_BASE 0xeff80000 41 #endif 42 43 #ifndef CONFIG_RESET_VECTOR_ADDRESS 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 45 #endif 46 47 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 48 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 49 #define CONFIG_FSL_IFC /* Enable IFC Support */ 50 #define CONFIG_PCI /* Enable PCI/PCIE */ 51 #define CONFIG_PCIE1 /* PCIE controler 1 */ 52 #define CONFIG_PCIE2 /* PCIE controler 2 */ 53 #define CONFIG_PCIE3 /* PCIE controler 3 */ 54 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 55 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 56 57 #define CONFIG_SYS_SRIO 58 #define CONFIG_SRIO1 /* SRIO port 1 */ 59 #define CONFIG_SRIO2 /* SRIO port 2 */ 60 #define CONFIG_SRIO_PCIE_BOOT_MASTER 61 62 #define CONFIG_FSL_LAW /* Use common FSL init code */ 63 64 #define CONFIG_ENV_OVERWRITE 65 66 #ifdef CONFIG_SYS_NO_FLASH 67 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 68 #define CONFIG_ENV_IS_NOWHERE 69 #endif 70 #else 71 #define CONFIG_FLASH_CFI_DRIVER 72 #define CONFIG_SYS_FLASH_CFI 73 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 74 #endif 75 76 #if defined(CONFIG_SPIFLASH) 77 #define CONFIG_SYS_EXTRA_ENV_RELOC 78 #define CONFIG_ENV_IS_IN_SPI_FLASH 79 #define CONFIG_ENV_SPI_BUS 0 80 #define CONFIG_ENV_SPI_CS 0 81 #define CONFIG_ENV_SPI_MAX_HZ 10000000 82 #define CONFIG_ENV_SPI_MODE 0 83 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 84 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 85 #define CONFIG_ENV_SECT_SIZE 0x10000 86 #elif defined(CONFIG_SDCARD) 87 #define CONFIG_SYS_EXTRA_ENV_RELOC 88 #define CONFIG_ENV_IS_IN_MMC 89 #define CONFIG_SYS_MMC_ENV_DEV 0 90 #define CONFIG_ENV_SIZE 0x2000 91 #define CONFIG_ENV_OFFSET (512 * 1097) 92 #elif defined(CONFIG_NAND) 93 #define CONFIG_SYS_EXTRA_ENV_RELOC 94 #define CONFIG_ENV_IS_IN_NAND 95 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 96 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 97 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 98 #define CONFIG_ENV_IS_IN_REMOTE 99 #define CONFIG_ENV_ADDR 0xffe20000 100 #define CONFIG_ENV_SIZE 0x2000 101 #elif defined(CONFIG_ENV_IS_NOWHERE) 102 #define CONFIG_ENV_SIZE 0x2000 103 #else 104 #define CONFIG_ENV_IS_IN_FLASH 105 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 106 #define CONFIG_ENV_SIZE 0x2000 107 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 108 #endif 109 110 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 111 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 112 113 #ifndef __ASSEMBLY__ 114 unsigned long get_board_sys_clk(void); 115 unsigned long get_board_ddr_clk(void); 116 #endif 117 118 /* 119 * These can be toggled for performance analysis, otherwise use default. 120 */ 121 #define CONFIG_SYS_CACHE_STASHING 122 #define CONFIG_BTB /* toggle branch predition */ 123 #define CONFIG_DDR_ECC 124 #ifdef CONFIG_DDR_ECC 125 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 126 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 127 #endif 128 129 #define CONFIG_ENABLE_36BIT_PHYS 130 131 #ifdef CONFIG_PHYS_64BIT 132 #define CONFIG_ADDR_MAP 133 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 134 #endif 135 136 #if 0 137 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 138 #endif 139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 140 #define CONFIG_SYS_MEMTEST_END 0x00400000 141 #define CONFIG_SYS_ALT_MEMTEST 142 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 143 144 /* 145 * Config the L3 Cache as L3 SRAM 146 */ 147 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 148 149 #ifdef CONFIG_PHYS_64BIT 150 #define CONFIG_SYS_DCSRBAR 0xf0000000 151 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 152 #endif 153 154 /* EEPROM */ 155 #define CONFIG_ID_EEPROM 156 #define CONFIG_SYS_I2C_EEPROM_NXID 157 #define CONFIG_SYS_EEPROM_BUS_NUM 0 158 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 159 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 160 161 /* 162 * DDR Setup 163 */ 164 #define CONFIG_VERY_BIG_RAM 165 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 166 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 167 168 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 169 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 170 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 171 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 172 173 #define CONFIG_DDR_SPD 174 #define CONFIG_FSL_DDR3 175 176 #define CONFIG_SYS_SPD_BUS_NUM 0 177 #define SPD_EEPROM_ADDRESS1 0x51 178 #define SPD_EEPROM_ADDRESS2 0x52 179 #define SPD_EEPROM_ADDRESS3 0x53 180 #define SPD_EEPROM_ADDRESS4 0x54 181 #define SPD_EEPROM_ADDRESS5 0x55 182 #define SPD_EEPROM_ADDRESS6 0x56 183 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 184 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 185 186 /* 187 * IFC Definitions 188 */ 189 #define CONFIG_SYS_FLASH_BASE 0xe0000000 190 #ifdef CONFIG_PHYS_64BIT 191 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 192 #else 193 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 194 #endif 195 196 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 197 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 198 + 0x8000000) | \ 199 CSPR_PORT_SIZE_16 | \ 200 CSPR_MSEL_NOR | \ 201 CSPR_V) 202 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 203 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 204 CSPR_PORT_SIZE_16 | \ 205 CSPR_MSEL_NOR | \ 206 CSPR_V) 207 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 208 /* NOR Flash Timing Params */ 209 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 210 211 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 212 FTIM0_NOR_TEADC(0x5) | \ 213 FTIM0_NOR_TEAHC(0x5)) 214 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 215 FTIM1_NOR_TRAD_NOR(0x1A) |\ 216 FTIM1_NOR_TSEQRAD_NOR(0x13)) 217 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 218 FTIM2_NOR_TCH(0x4) | \ 219 FTIM2_NOR_TWPH(0x0E) | \ 220 FTIM2_NOR_TWP(0x1c)) 221 #define CONFIG_SYS_NOR_FTIM3 0x0 222 223 #define CONFIG_SYS_FLASH_QUIET_TEST 224 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 225 226 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 227 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 228 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 229 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 230 231 #define CONFIG_SYS_FLASH_EMPTY_INFO 232 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 233 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 234 235 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 236 #define QIXIS_BASE 0xffdf0000 237 #define QIXIS_LBMAP_SWITCH 6 238 #define QIXIS_LBMAP_MASK 0x0f 239 #define QIXIS_LBMAP_SHIFT 0 240 #define QIXIS_LBMAP_DFLTBANK 0x00 241 #define QIXIS_LBMAP_ALTBANK 0x04 242 #define QIXIS_RST_CTL_RESET 0x83 243 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 244 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 245 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 246 #ifdef CONFIG_PHYS_64BIT 247 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 248 #else 249 #define QIXIS_BASE_PHYS QIXIS_BASE 250 #endif 251 252 #define CONFIG_SYS_CSPR3_EXT (0xf) 253 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 254 | CSPR_PORT_SIZE_8 \ 255 | CSPR_MSEL_GPCM \ 256 | CSPR_V) 257 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 258 #define CONFIG_SYS_CSOR3 0x0 259 /* QIXIS Timing parameters for IFC CS3 */ 260 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 261 FTIM0_GPCM_TEADC(0x0e) | \ 262 FTIM0_GPCM_TEAHC(0x0e)) 263 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 264 FTIM1_GPCM_TRAD(0x3f)) 265 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 266 FTIM2_GPCM_TCH(0x0) | \ 267 FTIM2_GPCM_TWP(0x1f)) 268 #define CONFIG_SYS_CS3_FTIM3 0x0 269 270 /* NAND Flash on IFC */ 271 #define CONFIG_NAND_FSL_IFC 272 #define CONFIG_SYS_NAND_BASE 0xff800000 273 #ifdef CONFIG_PHYS_64BIT 274 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 275 #else 276 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 277 #endif 278 279 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 280 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 281 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 282 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 283 | CSPR_V) 284 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 285 286 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 287 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 288 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 289 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 290 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 291 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 292 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 293 294 #define CONFIG_SYS_NAND_ONFI_DETECTION 295 296 /* ONFI NAND Flash mode0 Timing Params */ 297 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 298 FTIM0_NAND_TWP(0x18) | \ 299 FTIM0_NAND_TWCHT(0x07) | \ 300 FTIM0_NAND_TWH(0x0a)) 301 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 302 FTIM1_NAND_TWBE(0x39) | \ 303 FTIM1_NAND_TRR(0x0e) | \ 304 FTIM1_NAND_TRP(0x18)) 305 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 306 FTIM2_NAND_TREH(0x0a) | \ 307 FTIM2_NAND_TWHRE(0x1e)) 308 #define CONFIG_SYS_NAND_FTIM3 0x0 309 310 #define CONFIG_SYS_NAND_DDR_LAW 11 311 312 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 313 #define CONFIG_SYS_MAX_NAND_DEVICE 1 314 #define CONFIG_MTD_NAND_VERIFY_WRITE 315 #define CONFIG_CMD_NAND 316 317 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 318 319 #if defined(CONFIG_NAND) 320 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 321 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 322 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 323 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 324 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 325 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 326 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 327 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 328 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 329 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 330 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 331 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 332 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 333 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 334 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 335 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 336 #else 337 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 338 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 339 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 340 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 341 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 342 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 343 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 344 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 345 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 346 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 347 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 348 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 349 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 350 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 351 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 352 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 353 #endif 354 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 355 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 356 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 357 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 358 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 359 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 360 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 361 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 362 363 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 364 365 #if defined(CONFIG_RAMBOOT_PBL) 366 #define CONFIG_SYS_RAMBOOT 367 #endif 368 369 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 370 #define CONFIG_MISC_INIT_R 371 372 #define CONFIG_HWCONFIG 373 374 /* define to use L1 as initial stack */ 375 #define CONFIG_L1_INIT_RAM 376 #define CONFIG_SYS_INIT_RAM_LOCK 377 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 378 #ifdef CONFIG_PHYS_64BIT 379 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 381 /* The assembler doesn't like typecast */ 382 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 383 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 384 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 385 #else 386 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 389 #endif 390 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 391 392 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 393 GENERATED_GBL_DATA_SIZE) 394 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 395 396 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 397 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 398 399 /* Serial Port - controlled on board with jumper J8 400 * open - index 2 401 * shorted - index 1 402 */ 403 #define CONFIG_CONS_INDEX 1 404 #define CONFIG_SYS_NS16550 405 #define CONFIG_SYS_NS16550_SERIAL 406 #define CONFIG_SYS_NS16550_REG_SIZE 1 407 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 408 409 #define CONFIG_SYS_BAUDRATE_TABLE \ 410 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 411 412 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 413 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 414 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 415 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 416 417 /* Use the HUSH parser */ 418 #define CONFIG_SYS_HUSH_PARSER 419 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 420 421 /* pass open firmware flat tree */ 422 #define CONFIG_OF_LIBFDT 423 #define CONFIG_OF_BOARD_SETUP 424 #define CONFIG_OF_STDOUT_VIA_ALIAS 425 426 /* new uImage format support */ 427 #define CONFIG_FIT 428 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 429 430 /* I2C */ 431 #define CONFIG_SYS_I2C 432 #define CONFIG_SYS_I2C_FSL 433 #define CONFIG_SYS_FSL_I2C_SPEED 100000 434 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 435 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 436 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 437 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 438 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 439 440 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 441 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 442 443 #define I2C_MUX_CH_DEFAULT 0x8 444 #define I2C_MUX_CH_VOL_MONITOR 0xa 445 #define I2C_MUX_CH_VSC3316_FS 0xc 446 #define I2C_MUX_CH_VSC3316_BS 0xd 447 448 /* Voltage monitor on channel 2*/ 449 #define I2C_VOL_MONITOR_ADDR 0x40 450 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 451 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 452 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 453 454 /* VSC Crossbar switches */ 455 #define CONFIG_VSC_CROSSBAR 456 #define VSC3316_FSM_TX_ADDR 0x70 457 #define VSC3316_FSM_RX_ADDR 0x71 458 459 /* 460 * RapidIO 461 */ 462 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 463 #ifdef CONFIG_PHYS_64BIT 464 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 465 #else 466 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 467 #endif 468 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 469 470 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 471 #ifdef CONFIG_PHYS_64BIT 472 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 473 #else 474 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 475 #endif 476 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 477 478 /* 479 * for slave u-boot IMAGE instored in master memory space, 480 * PHYS must be aligned based on the SIZE 481 */ 482 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 483 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 484 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 485 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 486 /* 487 * for slave UCODE and ENV instored in master memory space, 488 * PHYS must be aligned based on the SIZE 489 */ 490 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 491 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 492 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 493 494 /* slave core release by master*/ 495 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 496 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 497 498 /* 499 * SRIO_PCIE_BOOT - SLAVE 500 */ 501 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 502 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 503 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 504 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 505 #endif 506 /* 507 * eSPI - Enhanced SPI 508 */ 509 #define CONFIG_FSL_ESPI 510 #define CONFIG_SPI_FLASH 511 #define CONFIG_SPI_FLASH_SST 512 #define CONFIG_CMD_SF 513 #define CONFIG_SF_DEFAULT_SPEED 10000000 514 #define CONFIG_SF_DEFAULT_MODE 0 515 516 /* 517 * General PCI 518 * Memory space is mapped 1-1, but I/O space must start from 0. 519 */ 520 521 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 522 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 523 #ifdef CONFIG_PHYS_64BIT 524 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 525 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 526 #else 527 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 528 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 529 #endif 530 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 531 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 532 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 533 #ifdef CONFIG_PHYS_64BIT 534 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 535 #else 536 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 537 #endif 538 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 539 540 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 541 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 542 #ifdef CONFIG_PHYS_64BIT 543 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 544 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 545 #else 546 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 547 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 548 #endif 549 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 550 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 551 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 552 #ifdef CONFIG_PHYS_64BIT 553 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 554 #else 555 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 556 #endif 557 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 558 559 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 560 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 561 #ifdef CONFIG_PHYS_64BIT 562 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 563 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 564 #else 565 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 566 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 567 #endif 568 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 569 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 570 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 571 #ifdef CONFIG_PHYS_64BIT 572 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 573 #else 574 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 575 #endif 576 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 577 578 /* controller 4, Base address 203000 */ 579 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 580 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 581 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 582 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 583 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 584 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 585 586 /* Qman/Bman */ 587 #ifndef CONFIG_NOBQFMAN 588 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 589 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 590 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 591 #ifdef CONFIG_PHYS_64BIT 592 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 593 #else 594 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 595 #endif 596 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 597 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 598 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 599 #ifdef CONFIG_PHYS_64BIT 600 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 601 #else 602 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 603 #endif 604 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 605 606 #define CONFIG_SYS_DPAA_FMAN 607 #define CONFIG_SYS_DPAA_PME 608 #define CONFIG_SYS_PMAN 609 #define CONFIG_SYS_DPAA_DCE 610 #define CONFIG_SYS_INTERLAKEN 611 612 /* Default address of microcode for the Linux Fman driver */ 613 #if defined(CONFIG_SPIFLASH) 614 /* 615 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 616 * env, so we got 0x110000. 617 */ 618 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 619 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 620 #elif defined(CONFIG_SDCARD) 621 /* 622 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 623 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 624 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 625 */ 626 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 627 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 628 #elif defined(CONFIG_NAND) 629 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 630 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 631 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 632 /* 633 * Slave has no ucode locally, it can fetch this from remote. When implementing 634 * in two corenet boards, slave's ucode could be stored in master's memory 635 * space, the address can be mapped from slave TLB->slave LAW-> 636 * slave SRIO or PCIE outbound window->master inbound window-> 637 * master LAW->the ucode address in master's memory space. 638 */ 639 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 640 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 641 #else 642 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 643 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 644 #endif 645 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 646 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 647 #endif /* CONFIG_NOBQFMAN */ 648 649 #ifdef CONFIG_SYS_DPAA_FMAN 650 #define CONFIG_FMAN_ENET 651 #define CONFIG_PHYLIB_10G 652 #define CONFIG_PHY_VITESSE 653 #define CONFIG_PHY_TERANETICS 654 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 655 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 656 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 657 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 658 #define FM1_10GEC1_PHY_ADDR 0x0 659 #define FM1_10GEC2_PHY_ADDR 0x1 660 #define FM2_10GEC1_PHY_ADDR 0x2 661 #define FM2_10GEC2_PHY_ADDR 0x3 662 #endif 663 664 #ifdef CONFIG_PCI 665 #define CONFIG_PCI_INDIRECT_BRIDGE 666 #define CONFIG_NET_MULTI 667 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 668 #define CONFIG_E1000 669 670 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 671 #define CONFIG_DOS_PARTITION 672 #endif /* CONFIG_PCI */ 673 674 /* SATA */ 675 #ifdef CONFIG_FSL_SATA_V2 676 #define CONFIG_LIBATA 677 #define CONFIG_FSL_SATA 678 679 #define CONFIG_SYS_SATA_MAX_DEVICE 2 680 #define CONFIG_SATA1 681 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 682 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 683 #define CONFIG_SATA2 684 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 685 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 686 687 #define CONFIG_LBA48 688 #define CONFIG_CMD_SATA 689 #define CONFIG_DOS_PARTITION 690 #define CONFIG_CMD_EXT2 691 #endif 692 693 #ifdef CONFIG_FMAN_ENET 694 #define CONFIG_MII /* MII PHY management */ 695 #define CONFIG_ETHPRIME "FM1@DTSEC1" 696 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 697 #endif 698 699 /* 700 * Environment 701 */ 702 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 703 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 704 705 /* 706 * Command line configuration. 707 */ 708 #include <config_cmd_default.h> 709 710 #define CONFIG_CMD_DHCP 711 #define CONFIG_CMD_ELF 712 #define CONFIG_CMD_ERRATA 713 #define CONFIG_CMD_GREPENV 714 #define CONFIG_CMD_IRQ 715 #define CONFIG_CMD_I2C 716 #define CONFIG_CMD_MII 717 #define CONFIG_CMD_PING 718 #define CONFIG_CMD_SETEXPR 719 720 #ifdef CONFIG_PCI 721 #define CONFIG_CMD_PCI 722 #define CONFIG_CMD_NET 723 #endif 724 725 /* 726 * USB 727 */ 728 #define CONFIG_CMD_USB 729 #define CONFIG_USB_STORAGE 730 #define CONFIG_USB_EHCI 731 #define CONFIG_USB_EHCI_FSL 732 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 733 #define CONFIG_CMD_EXT2 734 #define CONFIG_HAS_FSL_DR_USB 735 736 #define CONFIG_MMC 737 738 #ifdef CONFIG_MMC 739 #define CONFIG_FSL_ESDHC 740 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 741 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 742 #define CONFIG_CMD_MMC 743 #define CONFIG_GENERIC_MMC 744 #define CONFIG_CMD_EXT2 745 #define CONFIG_CMD_FAT 746 #define CONFIG_DOS_PARTITION 747 #endif 748 749 /* 750 * Miscellaneous configurable options 751 */ 752 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 753 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 754 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 755 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 756 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 757 #ifdef CONFIG_CMD_KGDB 758 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 759 #else 760 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 761 #endif 762 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 763 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 764 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 765 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 766 767 /* 768 * For booting Linux, the board info and command line data 769 * have to be in the first 64 MB of memory, since this is 770 * the maximum mapped by the Linux kernel during initialization. 771 */ 772 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 773 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 774 775 #ifdef CONFIG_CMD_KGDB 776 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 777 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 778 #endif 779 780 /* 781 * Environment Configuration 782 */ 783 #define CONFIG_ROOTPATH "/opt/nfsroot" 784 #define CONFIG_BOOTFILE "uImage" 785 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 786 787 /* default location for tftp and bootm */ 788 #define CONFIG_LOADADDR 1000000 789 790 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 791 792 #define CONFIG_BAUDRATE 115200 793 794 #define __USB_PHY_TYPE utmi 795 796 /* 797 * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be 798 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 799 * cacheline interleaving. It can be cacheline, page, bank, superbank. 800 * See doc/README.fsl-ddr for details. 801 */ 802 #ifdef CONFIG_PPC_T4240 803 #define CTRL_INTLV_PREFERED 3way_4KB 804 #else 805 #define CTRL_INTLV_PREFERED cacheline 806 #endif 807 808 #define CONFIG_EXTRA_ENV_SETTINGS \ 809 "hwconfig=fsl_ddr:" \ 810 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 811 "bank_intlv=auto;" \ 812 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 813 "netdev=eth0\0" \ 814 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 815 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 816 "tftpflash=tftpboot $loadaddr $uboot && " \ 817 "protect off $ubootaddr +$filesize && " \ 818 "erase $ubootaddr +$filesize && " \ 819 "cp.b $loadaddr $ubootaddr $filesize && " \ 820 "protect on $ubootaddr +$filesize && " \ 821 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 822 "consoledev=ttyS0\0" \ 823 "ramdiskaddr=2000000\0" \ 824 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 825 "fdtaddr=c00000\0" \ 826 "fdtfile=t4240qds/t4240qds.dtb\0" \ 827 "bdev=sda3\0" \ 828 "c=ffe\0" 829 830 /* For emulation this causes u-boot to jump to the start of the proof point 831 app code automatically */ 832 #define CONFIG_PROOF_POINTS \ 833 "setenv bootargs root=/dev/$bdev rw " \ 834 "console=$consoledev,$baudrate $othbootargs;" \ 835 "cpu 1 release 0x29000000 - - -;" \ 836 "cpu 2 release 0x29000000 - - -;" \ 837 "cpu 3 release 0x29000000 - - -;" \ 838 "cpu 4 release 0x29000000 - - -;" \ 839 "cpu 5 release 0x29000000 - - -;" \ 840 "cpu 6 release 0x29000000 - - -;" \ 841 "cpu 7 release 0x29000000 - - -;" \ 842 "go 0x29000000" 843 844 #define CONFIG_HVBOOT \ 845 "setenv bootargs config-addr=0x60000000; " \ 846 "bootm 0x01000000 - 0x00f00000" 847 848 #define CONFIG_ALU \ 849 "setenv bootargs root=/dev/$bdev rw " \ 850 "console=$consoledev,$baudrate $othbootargs;" \ 851 "cpu 1 release 0x01000000 - - -;" \ 852 "cpu 2 release 0x01000000 - - -;" \ 853 "cpu 3 release 0x01000000 - - -;" \ 854 "cpu 4 release 0x01000000 - - -;" \ 855 "cpu 5 release 0x01000000 - - -;" \ 856 "cpu 6 release 0x01000000 - - -;" \ 857 "cpu 7 release 0x01000000 - - -;" \ 858 "go 0x01000000" 859 860 #define CONFIG_LINUX \ 861 "setenv bootargs root=/dev/ram rw " \ 862 "console=$consoledev,$baudrate $othbootargs;" \ 863 "setenv ramdiskaddr 0x02000000;" \ 864 "setenv fdtaddr 0x00c00000;" \ 865 "setenv loadaddr 0x1000000;" \ 866 "bootm $loadaddr $ramdiskaddr $fdtaddr" 867 868 #define CONFIG_HDBOOT \ 869 "setenv bootargs root=/dev/$bdev rw " \ 870 "console=$consoledev,$baudrate $othbootargs;" \ 871 "tftp $loadaddr $bootfile;" \ 872 "tftp $fdtaddr $fdtfile;" \ 873 "bootm $loadaddr - $fdtaddr" 874 875 #define CONFIG_NFSBOOTCOMMAND \ 876 "setenv bootargs root=/dev/nfs rw " \ 877 "nfsroot=$serverip:$rootpath " \ 878 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 879 "console=$consoledev,$baudrate $othbootargs;" \ 880 "tftp $loadaddr $bootfile;" \ 881 "tftp $fdtaddr $fdtfile;" \ 882 "bootm $loadaddr - $fdtaddr" 883 884 #define CONFIG_RAMBOOTCOMMAND \ 885 "setenv bootargs root=/dev/ram rw " \ 886 "console=$consoledev,$baudrate $othbootargs;" \ 887 "tftp $ramdiskaddr $ramdiskfile;" \ 888 "tftp $loadaddr $bootfile;" \ 889 "tftp $fdtaddr $fdtfile;" \ 890 "bootm $loadaddr $ramdiskaddr $fdtaddr" 891 892 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 893 894 #ifdef CONFIG_SECURE_BOOT 895 #include <asm/fsl_secure_boot.h> 896 #endif 897 898 #endif /* __CONFIG_H */ 899