1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __T4QDS_H 11 #define __T4QDS_H 12 13 #define CONFIG_CMD_REGINFO 14 15 /* High Level Configuration Options */ 16 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 17 #define CONFIG_MP /* support multiple processors */ 18 19 #ifndef CONFIG_SYS_TEXT_BASE 20 #define CONFIG_SYS_TEXT_BASE 0xeff40000 21 #endif 22 23 #ifndef CONFIG_RESET_VECTOR_ADDRESS 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 25 #endif 26 27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 28 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 29 #define CONFIG_FSL_IFC /* Enable IFC Support */ 30 #define CONFIG_PCIE1 /* PCIE controller 1 */ 31 #define CONFIG_PCIE2 /* PCIE controller 2 */ 32 #define CONFIG_PCIE3 /* PCIE controller 3 */ 33 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 34 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 35 36 #define CONFIG_SYS_SRIO 37 #define CONFIG_SRIO1 /* SRIO port 1 */ 38 #define CONFIG_SRIO2 /* SRIO port 2 */ 39 40 #define CONFIG_ENV_OVERWRITE 41 42 /* 43 * These can be toggled for performance analysis, otherwise use default. 44 */ 45 #define CONFIG_SYS_CACHE_STASHING 46 #define CONFIG_BTB /* toggle branch predition */ 47 #ifdef CONFIG_DDR_ECC 48 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 49 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 50 #endif 51 52 #define CONFIG_ENABLE_36BIT_PHYS 53 54 #define CONFIG_ADDR_MAP 55 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 56 57 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 58 #define CONFIG_SYS_MEMTEST_END 0x00400000 59 #define CONFIG_SYS_ALT_MEMTEST 60 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 61 62 /* 63 * Config the L3 Cache as L3 SRAM 64 */ 65 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 66 #define CONFIG_SYS_L3_SIZE (512 << 10) 67 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 68 #ifdef CONFIG_RAMBOOT_PBL 69 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 70 #endif 71 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 72 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 73 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 74 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 75 76 #define CONFIG_SYS_DCSRBAR 0xf0000000 77 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 78 79 /* 80 * DDR Setup 81 */ 82 #define CONFIG_VERY_BIG_RAM 83 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 85 86 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 87 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 88 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 89 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 90 91 #define CONFIG_DDR_SPD 92 #define CONFIG_SYS_FSL_DDR3 93 94 /* 95 * IFC Definitions 96 */ 97 #define CONFIG_SYS_FLASH_BASE 0xe0000000 98 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 99 100 #ifdef CONFIG_SPL_BUILD 101 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 102 #else 103 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 104 #endif 105 106 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 107 #define CONFIG_MISC_INIT_R 108 109 #define CONFIG_HWCONFIG 110 111 /* define to use L1 as initial stack */ 112 #define CONFIG_L1_INIT_RAM 113 #define CONFIG_SYS_INIT_RAM_LOCK 114 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 115 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 116 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 117 /* The assembler doesn't like typecast */ 118 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 119 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 120 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 121 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 122 123 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 124 GENERATED_GBL_DATA_SIZE) 125 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 126 127 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 128 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 129 130 /* Serial Port - controlled on board with jumper J8 131 * open - index 2 132 * shorted - index 1 133 */ 134 #define CONFIG_CONS_INDEX 1 135 #define CONFIG_SYS_NS16550_SERIAL 136 #define CONFIG_SYS_NS16550_REG_SIZE 1 137 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 138 139 #define CONFIG_SYS_BAUDRATE_TABLE \ 140 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 141 142 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 143 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 144 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 145 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 146 147 /* I2C */ 148 #define CONFIG_SYS_I2C 149 #define CONFIG_SYS_I2C_FSL 150 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 151 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 152 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 153 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 154 155 /* 156 * RapidIO 157 */ 158 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 159 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 160 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 161 162 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 163 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 164 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 165 166 /* 167 * General PCI 168 * Memory space is mapped 1-1, but I/O space must start from 0. 169 */ 170 171 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 172 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 173 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 174 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 175 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 176 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 177 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 178 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 179 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 180 181 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 182 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 183 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 184 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 185 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 186 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 187 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 188 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 189 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 190 191 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 192 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 193 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 194 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 195 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 196 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 197 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 198 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 199 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 200 201 /* controller 4, Base address 203000 */ 202 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 203 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 204 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 205 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 206 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 207 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 208 209 #ifdef CONFIG_PCI 210 #define CONFIG_PCI_INDIRECT_BRIDGE 211 212 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 213 #define CONFIG_DOS_PARTITION 214 #endif /* CONFIG_PCI */ 215 216 /* SATA */ 217 #ifdef CONFIG_FSL_SATA_V2 218 #define CONFIG_LIBATA 219 #define CONFIG_FSL_SATA 220 221 #define CONFIG_SYS_SATA_MAX_DEVICE 2 222 #define CONFIG_SATA1 223 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 224 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 225 #define CONFIG_SATA2 226 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 227 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 228 229 #define CONFIG_LBA48 230 #define CONFIG_CMD_SATA 231 #define CONFIG_DOS_PARTITION 232 #endif 233 234 #ifdef CONFIG_FMAN_ENET 235 #define CONFIG_MII /* MII PHY management */ 236 #define CONFIG_ETHPRIME "FM1@DTSEC1" 237 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 238 #endif 239 240 /* 241 * Environment 242 */ 243 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 244 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 245 246 /* 247 * Command line configuration. 248 */ 249 #define CONFIG_CMD_ERRATA 250 #define CONFIG_CMD_IRQ 251 252 #ifdef CONFIG_PCI 253 #define CONFIG_CMD_PCI 254 #endif 255 256 /* 257 * Miscellaneous configurable options 258 */ 259 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 260 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 261 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 262 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 263 #ifdef CONFIG_CMD_KGDB 264 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 265 #else 266 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 267 #endif 268 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 269 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 270 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 271 272 /* 273 * For booting Linux, the board info and command line data 274 * have to be in the first 64 MB of memory, since this is 275 * the maximum mapped by the Linux kernel during initialization. 276 */ 277 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 278 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 279 280 #ifdef CONFIG_CMD_KGDB 281 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 282 #endif 283 284 /* 285 * Environment Configuration 286 */ 287 #define CONFIG_ROOTPATH "/opt/nfsroot" 288 #define CONFIG_BOOTFILE "uImage" 289 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 290 291 /* default location for tftp and bootm */ 292 #define CONFIG_LOADADDR 1000000 293 294 #define CONFIG_BAUDRATE 115200 295 296 #define CONFIG_HVBOOT \ 297 "setenv bootargs config-addr=0x60000000; " \ 298 "bootm 0x01000000 - 0x00f00000" 299 300 #endif /* __CONFIG_H */ 301