1 /* 2 * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * 4 * (C) Copyright 2007-2011 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * Tom Cubie <tangliang@allwinnertech.com> 7 * 8 * Configuration settings for the Allwinner sunxi series of boards. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef _SUNXI_COMMON_CONFIG_H 14 #define _SUNXI_COMMON_CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_SUNXI /* sunxi family */ 20 #ifdef CONFIG_SPL_BUILD 21 #ifndef CONFIG_SPL_FEL 22 #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ 23 #endif 24 #endif 25 26 #include <asm/arch/cpu.h> /* get chip and board defs */ 27 28 #define CONFIG_SYS_TEXT_BASE 0x4a000000 29 30 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM) 31 # define CONFIG_CMD_DM 32 #endif 33 34 /* 35 * Display CPU information 36 */ 37 #define CONFIG_DISPLAY_CPUINFO 38 39 /* Serial & console */ 40 #define CONFIG_SYS_NS16550 41 #define CONFIG_SYS_NS16550_SERIAL 42 /* ns16550 reg in the low bits of cpu reg */ 43 #define CONFIG_SYS_NS16550_REG_SIZE -4 44 #define CONFIG_SYS_NS16550_CLK 24000000 45 #define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE 46 #define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE 47 #define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE 48 #define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE 49 #define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE 50 51 /* DRAM Base */ 52 #define CONFIG_SYS_SDRAM_BASE 0x40000000 53 #define CONFIG_SYS_INIT_RAM_ADDR 0x0 54 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ 55 56 #define CONFIG_SYS_INIT_SP_OFFSET \ 57 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 58 #define CONFIG_SYS_INIT_SP_ADDR \ 59 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 60 61 #define CONFIG_NR_DRAM_BANKS 1 62 #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE 63 #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ 64 65 #ifdef CONFIG_AHCI 66 #define CONFIG_LIBATA 67 #define CONFIG_SCSI_AHCI 68 #define CONFIG_SCSI_AHCI_PLAT 69 #define CONFIG_SUNXI_AHCI 70 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 71 #define CONFIG_SYS_SCSI_MAX_LUN 1 72 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 73 CONFIG_SYS_SCSI_MAX_LUN) 74 #define CONFIG_CMD_SCSI 75 #endif 76 77 #define CONFIG_CMD_MEMORY 78 #define CONFIG_CMD_SETEXPR 79 80 #define CONFIG_SETUP_MEMORY_TAGS 81 #define CONFIG_CMDLINE_TAG 82 #define CONFIG_INITRD_TAG 83 84 /* mmc config */ 85 #if !defined(CONFIG_UART0_PORT_F) 86 #define CONFIG_MMC 87 #define CONFIG_GENERIC_MMC 88 #define CONFIG_CMD_MMC 89 #define CONFIG_MMC_SUNXI 90 #define CONFIG_MMC_SUNXI_SLOT 0 91 #define CONFIG_ENV_IS_IN_MMC 92 #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ 93 #endif 94 95 /* 4MB of malloc() pool */ 96 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) 97 98 /* 99 * Miscellaneous configurable options 100 */ 101 #define CONFIG_CMD_ECHO 102 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 103 #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ 104 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 105 #define CONFIG_SYS_GENERIC_BOARD 106 107 /* Boot Argument Buffer Size */ 108 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 109 110 #define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ 111 112 /* standalone support */ 113 #define CONFIG_STANDALONE_LOAD_ADDR 0x42000000 114 115 /* baudrate */ 116 #define CONFIG_BAUDRATE 115200 117 118 /* The stack sizes are set up in start.S using the settings below */ 119 #define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ 120 121 /* FLASH and environment organization */ 122 123 #define CONFIG_SYS_NO_FLASH 124 125 #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */ 126 #define CONFIG_IDENT_STRING " Allwinner Technology" 127 128 #define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */ 129 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 130 131 #include <config_cmd_default.h> 132 #undef CONFIG_CMD_FPGA 133 134 #define CONFIG_FAT_WRITE /* enable write access */ 135 136 #define CONFIG_SPL_FRAMEWORK 137 #define CONFIG_SPL_LIBCOMMON_SUPPORT 138 #define CONFIG_SPL_SERIAL_SUPPORT 139 #define CONFIG_SPL_LIBGENERIC_SUPPORT 140 141 #ifdef CONFIG_SPL_FEL 142 143 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds" 144 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi" 145 #define CONFIG_SPL_TEXT_BASE 0x2000 146 #define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */ 147 148 #else /* CONFIG_SPL */ 149 150 #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 151 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */ 152 153 #define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ 154 #define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */ 155 156 #define CONFIG_SPL_LIBDISK_SUPPORT 157 #define CONFIG_SPL_MMC_SUPPORT 158 159 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" 160 161 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */ 162 #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ 163 164 #endif /* CONFIG_SPL */ 165 166 /* end of 32 KiB in sram */ 167 #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ 168 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 169 #define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000 170 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */ 171 172 /* I2C */ 173 #define CONFIG_SPL_I2C_SUPPORT 174 #define CONFIG_SYS_I2C 175 #define CONFIG_SYS_I2C_MVTWSI 176 #define CONFIG_SYS_I2C_SPEED 400000 177 #define CONFIG_SYS_I2C_SLAVE 0x7f 178 #define CONFIG_CMD_I2C 179 180 /* PMU */ 181 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER 182 #define CONFIG_SPL_POWER_SUPPORT 183 #endif 184 185 #ifndef CONFIG_CONS_INDEX 186 #define CONFIG_CONS_INDEX 1 /* UART0 */ 187 #endif 188 189 /* GPIO */ 190 #define CONFIG_SUNXI_GPIO 191 #define CONFIG_SPL_GPIO_SUPPORT 192 #define CONFIG_CMD_GPIO 193 194 /* Ethernet support */ 195 #ifdef CONFIG_SUNXI_EMAC 196 #define CONFIG_MII /* MII PHY management */ 197 #endif 198 199 #ifdef CONFIG_SUNXI_GMAC 200 #define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */ 201 #define CONFIG_DW_AUTONEG 202 #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ 203 #define CONFIG_PHY_ADDR 1 204 #define CONFIG_MII /* MII PHY management */ 205 #define CONFIG_PHYLIB 206 #endif 207 208 #ifdef CONFIG_USB_EHCI 209 #define CONFIG_CMD_USB 210 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 211 #define CONFIG_USB_STORAGE 212 #endif 213 214 #if !defined CONFIG_ENV_IS_IN_MMC && \ 215 !defined CONFIG_ENV_IS_IN_NAND && \ 216 !defined CONFIG_ENV_IS_IN_FAT && \ 217 !defined CONFIG_ENV_IS_IN_SPI_FLASH 218 #define CONFIG_ENV_IS_NOWHERE 219 #endif 220 221 #define CONFIG_MISC_INIT_R 222 223 #ifndef CONFIG_SPL_BUILD 224 #include <config_distro_defaults.h> 225 226 /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, 227 * 1M script, 1M pxe and the ramdisk at the end */ 228 #define MEM_LAYOUT_ENV_SETTINGS \ 229 "bootm_size=0x10000000\0" \ 230 "kernel_addr_r=0x42000000\0" \ 231 "fdt_addr_r=0x43000000\0" \ 232 "scriptaddr=0x43100000\0" \ 233 "pxefile_addr_r=0x43200000\0" \ 234 "ramdisk_addr_r=0x43300000\0" 235 236 #ifdef CONFIG_MMC 237 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 238 #else 239 #define BOOT_TARGET_DEVICES_MMC(func) 240 #endif 241 242 #ifdef CONFIG_AHCI 243 #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) 244 #else 245 #define BOOT_TARGET_DEVICES_SCSI(func) 246 #endif 247 248 #ifdef CONFIG_USB_EHCI 249 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) 250 #else 251 #define BOOT_TARGET_DEVICES_USB(func) 252 #endif 253 254 #define BOOT_TARGET_DEVICES(func) \ 255 BOOT_TARGET_DEVICES_MMC(func) \ 256 BOOT_TARGET_DEVICES_SCSI(func) \ 257 BOOT_TARGET_DEVICES_USB(func) \ 258 func(PXE, pxe, na) \ 259 func(DHCP, dhcp, na) 260 261 #include <config_distro_bootcmd.h> 262 263 #define CONFIG_EXTRA_ENV_SETTINGS \ 264 MEM_LAYOUT_ENV_SETTINGS \ 265 "fdtfile=" CONFIG_FDTFILE "\0" \ 266 "console=ttyS0,115200\0" \ 267 BOOTENV 268 269 #else /* ifndef CONFIG_SPL_BUILD */ 270 #define CONFIG_EXTRA_ENV_SETTINGS 271 #endif 272 273 #endif /* _SUNXI_COMMON_CONFIG_H */ 274