1cba69eeeSIan Campbell /* 2cba69eeeSIan Campbell * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net> 3cba69eeeSIan Campbell * 4cba69eeeSIan Campbell * (C) Copyright 2007-2011 5cba69eeeSIan Campbell * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6cba69eeeSIan Campbell * Tom Cubie <tangliang@allwinnertech.com> 7cba69eeeSIan Campbell * 8cba69eeeSIan Campbell * Configuration settings for the Allwinner sunxi series of boards. 9cba69eeeSIan Campbell * 10cba69eeeSIan Campbell * SPDX-License-Identifier: GPL-2.0+ 11cba69eeeSIan Campbell */ 12cba69eeeSIan Campbell 13cba69eeeSIan Campbell #ifndef _SUNXI_COMMON_CONFIG_H 14cba69eeeSIan Campbell #define _SUNXI_COMMON_CONFIG_H 15cba69eeeSIan Campbell 16daf6d399SHans de Goede #include <asm/arch/cpu.h> 17e049fe28SHans de Goede #include <linux/stringify.h> 18e049fe28SHans de Goede 1977ef1369SSiarhei Siamashka #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT 2077ef1369SSiarhei Siamashka /* 2177ef1369SSiarhei Siamashka * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the 2277ef1369SSiarhei Siamashka * expense of restricting some features, so the regular machine id values can 2377ef1369SSiarhei Siamashka * be used. 2477ef1369SSiarhei Siamashka */ 2577ef1369SSiarhei Siamashka # define CONFIG_MACH_TYPE_COMPAT_REV 0 2677ef1369SSiarhei Siamashka #else 2777ef1369SSiarhei Siamashka /* 2877ef1369SSiarhei Siamashka * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels. 2977ef1369SSiarhei Siamashka * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass 3077ef1369SSiarhei Siamashka * beyond the machine id check. 3177ef1369SSiarhei Siamashka */ 3277ef1369SSiarhei Siamashka # define CONFIG_MACH_TYPE_COMPAT_REV 1 3377ef1369SSiarhei Siamashka #endif 3477ef1369SSiarhei Siamashka 35cba69eeeSIan Campbell /* Serial & console */ 36cba69eeeSIan Campbell #define CONFIG_SYS_NS16550_SERIAL 37cba69eeeSIan Campbell /* ns16550 reg in the low bits of cpu reg */ 38cba69eeeSIan Campbell #define CONFIG_SYS_NS16550_CLK 24000000 394fb60552SThomas Chou #ifndef CONFIG_DM_SERIAL 401a81cf83SSimon Glass # define CONFIG_SYS_NS16550_REG_SIZE -4 41cba69eeeSIan Campbell # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE 42cba69eeeSIan Campbell # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE 43cba69eeeSIan Campbell # define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE 44cba69eeeSIan Campbell # define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE 45c757a50bSChen-Yu Tsai # define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE 461a81cf83SSimon Glass #endif 47cba69eeeSIan Campbell 488a65f69cSPaul Kocialkowski /* CPU */ 49e4916e85SAndre Przywara #define COUNTER_FREQUENCY 24000000 508a65f69cSPaul Kocialkowski 51e049fe28SHans de Goede /* 52e049fe28SHans de Goede * The DRAM Base differs between some models. We cannot use macros for the 53e049fe28SHans de Goede * CONFIG_FOO defines which contain the DRAM base address since they end 54e049fe28SHans de Goede * up unexpanded in include/autoconf.mk . 55e049fe28SHans de Goede * 56e049fe28SHans de Goede * So we have to have this #ifdef #else #endif block for these. 57e049fe28SHans de Goede */ 58e049fe28SHans de Goede #ifdef CONFIG_MACH_SUN9I 59e049fe28SHans de Goede #define SDRAM_OFFSET(x) 0x2##x 60e049fe28SHans de Goede #define CONFIG_SYS_SDRAM_BASE 0x20000000 61e049fe28SHans de Goede #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */ 62e049fe28SHans de Goede #define CONFIG_SYS_TEXT_BASE 0x2a000000 63ff42d107SHans de Goede /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here 64ff42d107SHans de Goede * since it needs to fit in with the other values. By also #defining it 65ff42d107SHans de Goede * we get warnings if the Kconfig value mismatches. */ 66ff42d107SHans de Goede #define CONFIG_SPL_STACK_R_ADDR 0x2fe00000 67e049fe28SHans de Goede #define CONFIG_SPL_BSS_START_ADDR 0x2ff80000 68e049fe28SHans de Goede #else 69e049fe28SHans de Goede #define SDRAM_OFFSET(x) 0x4##x 70cba69eeeSIan Campbell #define CONFIG_SYS_SDRAM_BASE 0x40000000 71e049fe28SHans de Goede #define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ 72e049fe28SHans de Goede #define CONFIG_SYS_TEXT_BASE 0x4a000000 73ff42d107SHans de Goede /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here 74ff42d107SHans de Goede * since it needs to fit in with the other values. By also #defining it 75ff42d107SHans de Goede * we get warnings if the Kconfig value mismatches. */ 76ff42d107SHans de Goede #define CONFIG_SPL_STACK_R_ADDR 0x4fe00000 77e049fe28SHans de Goede #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 78e049fe28SHans de Goede #endif 79e049fe28SHans de Goede 80e049fe28SHans de Goede #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ 81e049fe28SHans de Goede 82bc613d85SAndre Przywara #ifdef CONFIG_SUNXI_HIGH_SRAM 8377fe9887SHans de Goede /* 8477fe9887SHans de Goede * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is 8577fe9887SHans de Goede * slightly bigger. Note that it is possible to map the first 32 KiB of the 8677fe9887SHans de Goede * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the 8777fe9887SHans de Goede * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and 8877fe9887SHans de Goede * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. 8977fe9887SHans de Goede */ 9077fe9887SHans de Goede #define CONFIG_SYS_INIT_RAM_ADDR 0x10000 91eb504fa1SAndre Przywara #define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */ 9277fe9887SHans de Goede #else 93cba69eeeSIan Campbell #define CONFIG_SYS_INIT_RAM_ADDR 0x0 94cba69eeeSIan Campbell #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ 9577fe9887SHans de Goede #endif 96cba69eeeSIan Campbell 97cba69eeeSIan Campbell #define CONFIG_SYS_INIT_SP_OFFSET \ 98cba69eeeSIan Campbell (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 99cba69eeeSIan Campbell #define CONFIG_SYS_INIT_SP_ADDR \ 100cba69eeeSIan Campbell (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 101cba69eeeSIan Campbell 102cba69eeeSIan Campbell #define CONFIG_NR_DRAM_BANKS 1 103cba69eeeSIan Campbell #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE 104cba69eeeSIan Campbell #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ 105cba69eeeSIan Campbell 106a6e50a88SIan Campbell #ifdef CONFIG_AHCI 107a6e50a88SIan Campbell #define CONFIG_LIBATA 108a6e50a88SIan Campbell #define CONFIG_SCSI_AHCI 109a6e50a88SIan Campbell #define CONFIG_SCSI_AHCI_PLAT 110a6e50a88SIan Campbell #define CONFIG_SUNXI_AHCI 1110751b138SBernhard Nortmann #define CONFIG_SYS_64BIT_LBA 112a6e50a88SIan Campbell #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 113a6e50a88SIan Campbell #define CONFIG_SYS_SCSI_MAX_LUN 1 114a6e50a88SIan Campbell #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 115a6e50a88SIan Campbell CONFIG_SYS_SCSI_MAX_LUN) 116c649e3c9SSimon Glass #define CONFIG_SCSI 117a6e50a88SIan Campbell #endif 118a6e50a88SIan Campbell 119cba69eeeSIan Campbell #define CONFIG_SETUP_MEMORY_TAGS 120cba69eeeSIan Campbell #define CONFIG_CMDLINE_TAG 121cba69eeeSIan Campbell #define CONFIG_INITRD_TAG 1229f852211SPaul Kocialkowski #define CONFIG_SERIAL_TAG 123cba69eeeSIan Campbell 124e5268616SHans de Goede #ifdef CONFIG_NAND_SUNXI 125a0dfa88bSBoris Brezillon #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 1264ccae81cSBoris Brezillon #define CONFIG_SYS_NAND_ONFI_DETECTION 1274ccae81cSBoris Brezillon #define CONFIG_SYS_MAX_NAND_DEVICE 8 128960caebaSPiotr Zierhoffer #endif 129960caebaSPiotr Zierhoffer 13019e99fb4SSiarhei Siamashka #ifdef CONFIG_SPL_SPI_SUNXI 13119e99fb4SSiarhei Siamashka #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 13219e99fb4SSiarhei Siamashka #endif 13319e99fb4SSiarhei Siamashka 134e24ea55cSIan Campbell /* mmc config */ 13544c79879SMaxime Ripard #ifdef CONFIG_MMC 136e24ea55cSIan Campbell #define CONFIG_MMC_SUNXI_SLOT 0 137*fb1c43ccSMaxime Ripard #endif 138*fb1c43ccSMaxime Ripard 139*fb1c43ccSMaxime Ripard #if defined(CONFIG_ENV_IS_IN_MMC) 140e24ea55cSIan Campbell #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ 141ae042bebSEmmanuel Vadot #define CONFIG_SYS_MMC_MAX_DEVICE 4 142ff2b47f6SChen-Yu Tsai #endif 143e24ea55cSIan Campbell 1445c965ed9SHans de Goede /* 64MB of malloc() pool */ 1455c965ed9SHans de Goede #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20)) 146cba69eeeSIan Campbell 147cba69eeeSIan Campbell /* 148cba69eeeSIan Campbell * Miscellaneous configurable options 149cba69eeeSIan Campbell */ 15006beadb0SIan Campbell #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 15106beadb0SIan Campbell #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ 152cba69eeeSIan Campbell #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 153cba69eeeSIan Campbell 154cba69eeeSIan Campbell /* Boot Argument Buffer Size */ 155cba69eeeSIan Campbell #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 156cba69eeeSIan Campbell 157cba69eeeSIan Campbell /* standalone support */ 158e049fe28SHans de Goede #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR 159cba69eeeSIan Campbell 160cba69eeeSIan Campbell /* baudrate */ 161cba69eeeSIan Campbell 162cba69eeeSIan Campbell /* The stack sizes are set up in start.S using the settings below */ 163cba69eeeSIan Campbell #define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ 164cba69eeeSIan Campbell 165cba69eeeSIan Campbell /* FLASH and environment organization */ 166cba69eeeSIan Campbell 167fa5e1020SBoris Brezillon #define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */ 168cba69eeeSIan Campbell 169cba69eeeSIan Campbell #define CONFIG_FAT_WRITE /* enable write access */ 170cba69eeeSIan Campbell 171cba69eeeSIan Campbell #define CONFIG_SPL_FRAMEWORK 172cba69eeeSIan Campbell 173eb77f5c9SAndre Przywara #ifndef CONFIG_ARM64 /* AArch64 FEL support is not ready yet */ 174942cb0b6SSimon Glass #define CONFIG_SPL_BOARD_LOAD_IMAGE 175eb77f5c9SAndre Przywara #endif 176942cb0b6SSimon Glass 177bc613d85SAndre Przywara #ifdef CONFIG_SUNXI_HIGH_SRAM 178b19236fdSSiarhei Siamashka #define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */ 179bc613d85SAndre Przywara #define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB */ 180bc613d85SAndre Przywara #define LOW_LEVEL_SRAM_STACK 0x00018000 181d96ebc46SSiarhei Siamashka #else 182b19236fdSSiarhei Siamashka #define CONFIG_SPL_TEXT_BASE 0x40 /* sram start+header */ 183b19236fdSSiarhei Siamashka #define CONFIG_SPL_MAX_SIZE 0x5fc0 /* 24KB on sun4i/sun7i */ 184bc613d85SAndre Przywara #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ 185d96ebc46SSiarhei Siamashka #endif 18650827a59SIan Campbell 187bc613d85SAndre Przywara #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 188bc613d85SAndre Przywara 189d96ebc46SSiarhei Siamashka #ifndef CONFIG_ARM64 19050827a59SIan Campbell #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" 191d96ebc46SSiarhei Siamashka #endif 19250827a59SIan Campbell 19350827a59SIan Campbell #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ 19450827a59SIan Campbell 195cba69eeeSIan Campbell 1966620377eSHans de Goede /* I2C */ 1970d8382aeSJelle van der Waa #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 1980d8382aeSJelle van der Waa defined CONFIG_SY8106A_POWER 199ad40610bSHans de Goede #endif 200ad40610bSHans de Goede 2016c739c5dSPaul Kocialkowski #if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ 2026c739c5dSPaul Kocialkowski defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ 2039d082687SJelle van der Waa defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE 2048b2db32aSHans de Goede #define CONFIG_SYS_I2C 2056620377eSHans de Goede #define CONFIG_SYS_I2C_MVTWSI 2066620377eSHans de Goede #define CONFIG_SYS_I2C_SPEED 400000 2076620377eSHans de Goede #define CONFIG_SYS_I2C_SLAVE 0x7f 2088b2db32aSHans de Goede #endif 20955410089SHans de Goede 21055410089SHans de Goede #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 21155410089SHans de Goede #define CONFIG_SYS_I2C_SOFT 21255410089SHans de Goede #define CONFIG_SYS_I2C_SOFT_SPEED 50000 21355410089SHans de Goede #define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 21455410089SHans de Goede /* We use pin names in Kconfig and sunxi_name_to_gpio() */ 21555410089SHans de Goede #define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda 21655410089SHans de Goede #define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl 21755410089SHans de Goede #ifndef __ASSEMBLY__ 21855410089SHans de Goede extern int soft_i2c_gpio_sda; 21955410089SHans de Goede extern int soft_i2c_gpio_scl; 22055410089SHans de Goede #endif 2211fc42018SHans de Goede #define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */ 2221fc42018SHans de Goede #define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */ 2231fc42018SHans de Goede #else 2241fc42018SHans de Goede #define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */ 2251fc42018SHans de Goede #define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ 22655410089SHans de Goede #endif 22755410089SHans de Goede 22814bc66bdSHenrik Nordstrom /* PMU */ 22995ab8feeSvishnupatekar #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 2300d8382aeSJelle van der Waa defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \ 2310d8382aeSJelle van der Waa defined CONFIG_SY8106A_POWER 23214bc66bdSHenrik Nordstrom #endif 23314bc66bdSHenrik Nordstrom 234f84269c5SHans de Goede #ifndef CONFIG_CONS_INDEX 235cba69eeeSIan Campbell #define CONFIG_CONS_INDEX 1 /* UART0 */ 236f84269c5SHans de Goede #endif 237cba69eeeSIan Campbell 238a5da3c83SHans de Goede #ifdef CONFIG_REQUIRE_SERIAL_CONSOLE 239f3133962SHans de Goede #if CONFIG_CONS_INDEX == 1 240f3133962SHans de Goede #ifdef CONFIG_MACH_SUN9I 241f3133962SHans de Goede #define OF_STDOUT_PATH "/soc/serial@07000000:115200" 242f3133962SHans de Goede #else 243f3133962SHans de Goede #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28000:115200" 244f3133962SHans de Goede #endif 245f3133962SHans de Goede #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) 246f3133962SHans de Goede #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200" 2475cd83b11SLaurent Itti #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) 2485cd83b11SLaurent Itti #define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200" 249f3133962SHans de Goede #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) 250f3133962SHans de Goede #define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200" 251f3133962SHans de Goede #else 252f3133962SHans de Goede #error Unsupported console port nr. Please fix stdout-path in sunxi-common.h. 253f3133962SHans de Goede #endif 254a5da3c83SHans de Goede #endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */ 255f3133962SHans de Goede 256abce2c62SIan Campbell /* GPIO */ 257abce2c62SIan Campbell #define CONFIG_SUNXI_GPIO 258abce2c62SIan Campbell 2597f2c521fSLuc Verhaegen #ifdef CONFIG_VIDEO 2607f2c521fSLuc Verhaegen /* 2615633a296SHans de Goede * The amount of RAM to keep free at the top of RAM when relocating u-boot, 2625633a296SHans de Goede * to use as framebuffer. This must be a multiple of 4096. 2637f2c521fSLuc Verhaegen */ 2645c965ed9SHans de Goede #define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20) 2657f2c521fSLuc Verhaegen 2662d7a084bSLuc Verhaegen /* Do we want to initialize a simple FB? */ 2672d7a084bSLuc Verhaegen #define CONFIG_VIDEO_DT_SIMPLEFB 2682d7a084bSLuc Verhaegen 2697f2c521fSLuc Verhaegen #define CONFIG_VIDEO_SUNXI 2707f2c521fSLuc Verhaegen 2717f2c521fSLuc Verhaegen #define CONFIG_VIDEO_LOGO 272be8ec633SHans de Goede #define CONFIG_VIDEO_STD_TIMINGS 27375481607SHans de Goede #define CONFIG_I2C_EDID 27458332f89SHans de Goede #define VIDEO_LINE_LEN (pGD->plnSizeX) 2757f2c521fSLuc Verhaegen 2767f2c521fSLuc Verhaegen /* allow both serial and cfb console. */ 2777f2c521fSLuc Verhaegen /* stop x86 thinking in cfbconsole from trying to init a pc keyboard */ 2787f2c521fSLuc Verhaegen 2797f2c521fSLuc Verhaegen #endif /* CONFIG_VIDEO */ 2807f2c521fSLuc Verhaegen 281c26fb9dbSHans de Goede /* Ethernet support */ 282c26fb9dbSHans de Goede #ifdef CONFIG_SUNXI_EMAC 2838145dea4SHans de Goede #define CONFIG_PHY_ADDR 1 284c26fb9dbSHans de Goede #define CONFIG_MII /* MII PHY management */ 2858145dea4SHans de Goede #define CONFIG_PHYLIB 286c26fb9dbSHans de Goede #endif 287c26fb9dbSHans de Goede 2885835823dSIan Campbell #ifdef CONFIG_SUNXI_GMAC 2895835823dSIan Campbell #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ 2905835823dSIan Campbell #define CONFIG_PHY_ADDR 1 2915835823dSIan Campbell #define CONFIG_MII /* MII PHY management */ 2921eae8f66SHans de Goede #define CONFIG_PHY_REALTEK 2935835823dSIan Campbell #endif 2945835823dSIan Campbell 2952582ca0dSPaul Kocialkowski #ifdef CONFIG_USB_EHCI_HCD 2966a72e804SHans de Goede #define CONFIG_USB_OHCI_NEW 2976a72e804SHans de Goede #define CONFIG_USB_OHCI_SUNXI 2986a72e804SHans de Goede #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 2993584f30cSRoman Byshko #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 3001a800f7aSHans de Goede #endif 3011a800f7aSHans de Goede 3021a800f7aSHans de Goede #ifdef CONFIG_USB_MUSB_SUNXI 30395de1e2fSPaul Kocialkowski #define CONFIG_USB_MUSB_PIO_ONLY 3041a800f7aSHans de Goede #endif 3051a800f7aSHans de Goede 306b21144ebSPaul Kocialkowski #ifdef CONFIG_USB_MUSB_GADGET 307aaa4a9e3SSam Protsenko #define CONFIG_USB_FUNCTION_FASTBOOT 308aaa4a9e3SSam Protsenko #define CONFIG_USB_FUNCTION_MASS_STORAGE 309b21144ebSPaul Kocialkowski #endif 310b21144ebSPaul Kocialkowski 311b21144ebSPaul Kocialkowski #ifdef CONFIG_USB_FUNCTION_FASTBOOT 312b21144ebSPaul Kocialkowski #define CONFIG_CMD_FASTBOOT 313b21144ebSPaul Kocialkowski #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR 314b21144ebSPaul Kocialkowski #define CONFIG_FASTBOOT_BUF_SIZE 0x2000000 315bac83fb0SMaxime Ripard #define CONFIG_ANDROID_BOOT_IMAGE 316b21144ebSPaul Kocialkowski 317b21144ebSPaul Kocialkowski #define CONFIG_FASTBOOT_FLASH 31844c79879SMaxime Ripard 31944c79879SMaxime Ripard #ifdef CONFIG_MMC 320b21144ebSPaul Kocialkowski #define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 321b21144ebSPaul Kocialkowski #endif 32244c79879SMaxime Ripard #endif 323b21144ebSPaul Kocialkowski 324b21144ebSPaul Kocialkowski #ifdef CONFIG_USB_FUNCTION_MASS_STORAGE 325b21144ebSPaul Kocialkowski #endif 326b21144ebSPaul Kocialkowski 32786b49093SHans de Goede #ifdef CONFIG_USB_KEYBOARD 32886b49093SHans de Goede #define CONFIG_PREBOOT 329eab9433aSHans de Goede #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE 33086b49093SHans de Goede #endif 33186b49093SHans de Goede 332b41d7d05SJonathan Liu #define CONFIG_MISC_INIT_R 333b41d7d05SJonathan Liu 334cba69eeeSIan Campbell #ifndef CONFIG_SPL_BUILD 335cba69eeeSIan Campbell #include <config_distro_defaults.h> 3362ec3a612SHans de Goede 337671f9ad8SAndre Przywara #ifdef CONFIG_ARM64 338671f9ad8SAndre Przywara /* 339671f9ad8SAndre Przywara * Boards seem to come with at least 512MB of DRAM. 340671f9ad8SAndre Przywara * The kernel should go at 512K, which is the default text offset (that will 341671f9ad8SAndre Przywara * be adjusted at runtime if needed). 342671f9ad8SAndre Przywara * There is no compression for arm64 kernels (yet), so leave some space 343671f9ad8SAndre Przywara * for really big kernels, say 256MB for now. 344671f9ad8SAndre Przywara * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd. 345671f9ad8SAndre Przywara * Align the initrd to a 2MB page. 346671f9ad8SAndre Przywara */ 347671f9ad8SAndre Przywara #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000)) 348671f9ad8SAndre Przywara #define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) 349671f9ad8SAndre Przywara #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) 350671f9ad8SAndre Przywara #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) 351671f9ad8SAndre Przywara #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) 352671f9ad8SAndre Przywara 353671f9ad8SAndre Przywara #else 3548c95c556SHans de Goede /* 3555c965ed9SHans de Goede * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. 3568c95c556SHans de Goede * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, 3578c95c556SHans de Goede * 1M script, 1M pxe and the ramdisk at the end. 3588c95c556SHans de Goede */ 3592a909c5fSSiarhei Siamashka 3602a909c5fSSiarhei Siamashka #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) 3612a909c5fSSiarhei Siamashka #define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) 3622a909c5fSSiarhei Siamashka #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) 3632a909c5fSSiarhei Siamashka #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) 3642a909c5fSSiarhei Siamashka #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000)) 365671f9ad8SAndre Przywara #endif 3662a909c5fSSiarhei Siamashka 367846e3254SHans de Goede #define MEM_LAYOUT_ENV_SETTINGS \ 3685c965ed9SHans de Goede "bootm_size=0xa000000\0" \ 3692a909c5fSSiarhei Siamashka "kernel_addr_r=" KERNEL_ADDR_R "\0" \ 3702a909c5fSSiarhei Siamashka "fdt_addr_r=" FDT_ADDR_R "\0" \ 3712a909c5fSSiarhei Siamashka "scriptaddr=" SCRIPT_ADDR_R "\0" \ 3722a909c5fSSiarhei Siamashka "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ 3732a909c5fSSiarhei Siamashka "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" 3742a909c5fSSiarhei Siamashka 3752a909c5fSSiarhei Siamashka #define DFU_ALT_INFO_RAM \ 3762a909c5fSSiarhei Siamashka "dfu_alt_info_ram=" \ 3772a909c5fSSiarhei Siamashka "kernel ram " KERNEL_ADDR_R " 0x1000000;" \ 3782a909c5fSSiarhei Siamashka "fdt ram " FDT_ADDR_R " 0x100000;" \ 3792a909c5fSSiarhei Siamashka "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" 380846e3254SHans de Goede 38141f8e9f5SChen-Yu Tsai #ifdef CONFIG_MMC 38241f8e9f5SChen-Yu Tsai #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 3835a37a400SKarsten Merker #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 3845a37a400SKarsten Merker #define BOOT_TARGET_DEVICES_MMC_EXTRA(func) func(MMC, mmc, 1) 3855a37a400SKarsten Merker #else 3865a37a400SKarsten Merker #define BOOT_TARGET_DEVICES_MMC_EXTRA(func) 3875a37a400SKarsten Merker #endif 38841f8e9f5SChen-Yu Tsai #else 38941f8e9f5SChen-Yu Tsai #define BOOT_TARGET_DEVICES_MMC(func) 3905a37a400SKarsten Merker #define BOOT_TARGET_DEVICES_MMC_EXTRA(func) 39141f8e9f5SChen-Yu Tsai #endif 39241f8e9f5SChen-Yu Tsai 3932ec3a612SHans de Goede #ifdef CONFIG_AHCI 3942ec3a612SHans de Goede #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) 3952ec3a612SHans de Goede #else 3962ec3a612SHans de Goede #define BOOT_TARGET_DEVICES_SCSI(func) 3972ec3a612SHans de Goede #endif 3982ec3a612SHans de Goede 3992582ca0dSPaul Kocialkowski #ifdef CONFIG_USB_STORAGE 400859b3f14SChen-Yu Tsai #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) 401859b3f14SChen-Yu Tsai #else 402859b3f14SChen-Yu Tsai #define BOOT_TARGET_DEVICES_USB(func) 403859b3f14SChen-Yu Tsai #endif 404859b3f14SChen-Yu Tsai 405f3b589c0SBernhard Nortmann /* FEL boot support, auto-execute boot.scr if a script address was provided */ 406f3b589c0SBernhard Nortmann #define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ 407f3b589c0SBernhard Nortmann "bootcmd_fel=" \ 408f3b589c0SBernhard Nortmann "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ 409f3b589c0SBernhard Nortmann "echo '(FEL boot)'; " \ 410f3b589c0SBernhard Nortmann "source ${fel_scriptaddr}; " \ 411f3b589c0SBernhard Nortmann "fi\0" 412f3b589c0SBernhard Nortmann #define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ 413f3b589c0SBernhard Nortmann "fel " 414f3b589c0SBernhard Nortmann 4152ec3a612SHans de Goede #define BOOT_TARGET_DEVICES(func) \ 416f3b589c0SBernhard Nortmann func(FEL, fel, na) \ 41741f8e9f5SChen-Yu Tsai BOOT_TARGET_DEVICES_MMC(func) \ 4185a37a400SKarsten Merker BOOT_TARGET_DEVICES_MMC_EXTRA(func) \ 4192ec3a612SHans de Goede BOOT_TARGET_DEVICES_SCSI(func) \ 420859b3f14SChen-Yu Tsai BOOT_TARGET_DEVICES_USB(func) \ 4212ec3a612SHans de Goede func(PXE, pxe, na) \ 4222ec3a612SHans de Goede func(DHCP, dhcp, na) 4232ec3a612SHans de Goede 4243b824025SHans de Goede #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT 4253b824025SHans de Goede #define BOOTCMD_SUNXI_COMPAT \ 4263b824025SHans de Goede "bootcmd_sunxi_compat=" \ 4273b824025SHans de Goede "setenv root /dev/mmcblk0p3 rootwait; " \ 4283b824025SHans de Goede "if ext2load mmc 0 0x44000000 uEnv.txt; then " \ 4293b824025SHans de Goede "echo Loaded environment from uEnv.txt; " \ 4303b824025SHans de Goede "env import -t 0x44000000 ${filesize}; " \ 4313b824025SHans de Goede "fi; " \ 4323b824025SHans de Goede "setenv bootargs console=${console} root=${root} ${extraargs}; " \ 4333b824025SHans de Goede "ext2load mmc 0 0x43000000 script.bin && " \ 4343b824025SHans de Goede "ext2load mmc 0 0x48000000 uImage && " \ 4353b824025SHans de Goede "bootm 0x48000000\0" 4363b824025SHans de Goede #else 4373b824025SHans de Goede #define BOOTCMD_SUNXI_COMPAT 4383b824025SHans de Goede #endif 4393b824025SHans de Goede 4402ec3a612SHans de Goede #include <config_distro_bootcmd.h> 4412ec3a612SHans de Goede 44286b49093SHans de Goede #ifdef CONFIG_USB_KEYBOARD 44386b49093SHans de Goede #define CONSOLE_STDIN_SETTINGS \ 44486b49093SHans de Goede "preboot=usb start\0" \ 44586b49093SHans de Goede "stdin=serial,usbkbd\0" 44686b49093SHans de Goede #else 4477f2c521fSLuc Verhaegen #define CONSOLE_STDIN_SETTINGS \ 4487f2c521fSLuc Verhaegen "stdin=serial\0" 44986b49093SHans de Goede #endif 4507f2c521fSLuc Verhaegen 4517f2c521fSLuc Verhaegen #ifdef CONFIG_VIDEO 4527f2c521fSLuc Verhaegen #define CONSOLE_STDOUT_SETTINGS \ 4537f2c521fSLuc Verhaegen "stdout=serial,vga\0" \ 4547f2c521fSLuc Verhaegen "stderr=serial,vga\0" 4557f2c521fSLuc Verhaegen #else 4567f2c521fSLuc Verhaegen #define CONSOLE_STDOUT_SETTINGS \ 4577f2c521fSLuc Verhaegen "stdout=serial\0" \ 4587f2c521fSLuc Verhaegen "stderr=serial\0" 4597f2c521fSLuc Verhaegen #endif 4607f2c521fSLuc Verhaegen 4617f2c521fSLuc Verhaegen #define CONSOLE_ENV_SETTINGS \ 4627f2c521fSLuc Verhaegen CONSOLE_STDIN_SETTINGS \ 4637f2c521fSLuc Verhaegen CONSOLE_STDOUT_SETTINGS 4647f2c521fSLuc Verhaegen 4652ec3a612SHans de Goede #define CONFIG_EXTRA_ENV_SETTINGS \ 4667f2c521fSLuc Verhaegen CONSOLE_ENV_SETTINGS \ 467846e3254SHans de Goede MEM_LAYOUT_ENV_SETTINGS \ 4682a909c5fSSiarhei Siamashka DFU_ALT_INFO_RAM \ 46925acd33fSHans de Goede "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ 470846e3254SHans de Goede "console=ttyS0,115200\0" \ 4713b824025SHans de Goede BOOTCMD_SUNXI_COMPAT \ 4722ec3a612SHans de Goede BOOTENV 4732ec3a612SHans de Goede 4742ec3a612SHans de Goede #else /* ifndef CONFIG_SPL_BUILD */ 4752ec3a612SHans de Goede #define CONFIG_EXTRA_ENV_SETTINGS 476cba69eeeSIan Campbell #endif 477cba69eeeSIan Campbell 478cba69eeeSIan Campbell #endif /* _SUNXI_COMMON_CONFIG_H */ 479