1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * Wolfgang Denk <wd@denx.de> 6 * Copyright 2004 Freescale Semiconductor. 7 * (C) Copyright 2002,2003 Motorola,Inc. 8 * Xianghua Xiao <X.Xiao@motorola.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 /* 30 * Socrates 31 */ 32 33 #ifndef __CONFIG_H 34 #define __CONFIG_H 35 36 /* new uImage format support */ 37 #define CONFIG_FIT 1 38 #define CONFIG_OF_LIBFDT 1 39 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 40 41 /* High Level Configuration Options */ 42 #define CONFIG_BOOKE 1 /* BOOKE */ 43 #define CONFIG_E500 1 /* BOOKE e500 family */ 44 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 45 #define CONFIG_MPC8544 1 46 #define CONFIG_SOCRATES 1 47 48 #define CONFIG_PCI 49 50 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51 52 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ 53 #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ 54 55 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 56 57 /* 58 * Only possible on E500 Version 2 or newer cores. 59 */ 60 #define CONFIG_ENABLE_36BIT_PHYS 1 61 62 /* 63 * sysclk for MPC85xx 64 * 65 * Two valid values are: 66 * 33000000 67 * 66000000 68 * 69 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 70 * is likely the desired value here, so that is now the default. 71 * The board, however, can run at 66MHz. In any event, this value 72 * must match the settings of some switches. Details can be found 73 * in the README.mpc85xxads. 74 */ 75 76 #ifndef CONFIG_SYS_CLK_FREQ 77 #define CONFIG_SYS_CLK_FREQ 66666666 78 #endif 79 80 /* 81 * These can be toggled for performance analysis, otherwise use default. 82 */ 83 #define CONFIG_L2_CACHE /* toggle L2 cache */ 84 #define CONFIG_BTB /* toggle branch predition */ 85 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 86 87 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 88 89 #undef CFG_DRAM_TEST /* memory test, takes time */ 90 #define CFG_MEMTEST_START 0x00400000 91 #define CFG_MEMTEST_END 0x00C00000 92 93 /* 94 * Base addresses -- Note these are effective addresses where the 95 * actual resources get mapped (not physical addresses) 96 */ 97 #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ 98 #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ 99 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 100 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 101 102 /* DDR Setup */ 103 #define CONFIG_FSL_DDR2 104 #undef CONFIG_FSL_DDR_INTERACTIVE 105 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 106 #define CONFIG_DDR_SPD 107 108 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 109 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 110 111 #define CFG_DDR_SDRAM_BASE 0x00000000 112 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 113 #define CONFIG_VERY_BIG_RAM 114 115 #define CONFIG_NUM_DDR_CONTROLLERS 1 116 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 117 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 118 119 /* I2C addresses of SPD EEPROMs */ 120 #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ 121 122 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ 123 124 /* Hardcoded values, to use instead of SPD */ 125 #define CFG_DDR_CS0_BNDS 0x0000000f 126 #define CFG_DDR_CS0_CONFIG 0x80010102 127 #define CFG_DDR_TIMING_0 0x00260802 128 #define CFG_DDR_TIMING_1 0x3935D322 129 #define CFG_DDR_TIMING_2 0x14904CC8 130 #define CFG_DDR_MODE 0x00480432 131 #define CFG_DDR_INTERVAL 0x030C0100 132 #define CFG_DDR_CONFIG_2 0x04400000 133 #define CFG_DDR_CONFIG 0xC3008000 134 #define CFG_DDR_CLK_CONTROL 0x03800000 135 #define CFG_SDRAM_SIZE 256 /* in Megs */ 136 137 /* 138 * Flash on the LocalBus 139 */ 140 #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 141 142 #define CFG_FLASH0 0xFE000000 143 #define CFG_FLASH1 0xFC000000 144 #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } 145 146 #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ 147 #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ 148 149 #define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */ 150 #define CFG_OR0_PRELIM 0xfe000030 /* 32MB Flash */ 151 #define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */ 152 #define CFG_OR1_PRELIM 0xfe000030 /* 32MB Flash */ 153 154 #define CFG_FLASH_CFI /* flash is CFI compat. */ 155 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ 156 157 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 158 #define CFG_MAX_FLASH_SECT 256 /* sectors per device */ 159 #undef CFG_FLASH_CHECKSUM 160 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 161 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 162 163 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 164 165 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 166 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 167 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 168 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ 169 170 #define CONFIG_L1_INIT_RAM 171 #define CFG_INIT_RAM_LOCK 1 172 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 173 #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ 174 175 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ 176 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 177 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 178 179 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ 180 #define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ 181 182 /* FPGA and NAND */ 183 #define CFG_FPGA_BASE 0xc0000000 184 #define CFG_FPGA_SIZE 0x00100000 /* 1 MB */ 185 #define CFG_HMI_BASE 0xc0010000 186 #define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ 187 #define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ 188 189 #define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) 190 #define CFG_MAX_NAND_DEVICE 1 191 #define NAND_MAX_CHIPS 1 192 #define CONFIG_CMD_NAND 193 194 /* LIME GDC */ 195 #define CFG_LIME_BASE 0xc8000000 196 #define CFG_LIME_SIZE 0x04000000 /* 64 MB */ 197 #define CFG_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ 198 #define CFG_OR2_PRELIM 0xfc000000 /* 64 MB */ 199 200 #define CONFIG_VIDEO 201 #define CONFIG_VIDEO_MB862xx 202 #define CONFIG_CFB_CONSOLE 203 #define CONFIG_VIDEO_LOGO 204 #define CONFIG_VIDEO_BMP_LOGO 205 #define CONFIG_CONSOLE_EXTRA_INFO 206 #define VIDEO_FB_16BPP_PIXEL_SWAP 207 #define CONFIG_VGA_AS_SINGLE_DEVICE 208 #define CFG_CONSOLE_IS_IN_ENV 209 #define CONFIG_VIDEO_SW_CURSOR 210 #define CONFIG_SPLASH_SCREEN 211 #define CONFIG_VIDEO_BMP_GZIP 212 #define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ 213 214 /* Serial Port */ 215 216 #define CONFIG_CONS_INDEX 1 217 #undef CONFIG_SERIAL_SOFTWARE_FIFO 218 #define CFG_NS16550 219 #define CFG_NS16550_SERIAL 220 #define CFG_NS16550_REG_SIZE 1 221 #define CFG_NS16550_CLK get_bus_freq(0) 222 223 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 224 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 225 226 #define CONFIG_BAUDRATE 115200 227 228 #define CFG_BAUDRATE_TABLE \ 229 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 230 231 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 232 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ 233 #ifdef CFG_HUSH_PARSER 234 #define CFG_PROMPT_HUSH_PS2 "> " 235 #endif 236 237 238 /* 239 * I2C 240 */ 241 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 242 #define CONFIG_HARD_I2C /* I2C with hardware support */ 243 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 244 #define CFG_I2C_SPEED 102124 /* I2C speed and slave address */ 245 #define CFG_I2C_SLAVE 0x7F 246 #define CFG_I2C_OFFSET 0x3000 247 248 #define CONFIG_I2C_MULTI_BUS 249 #define CONFIG_I2C_CMD_TREE 250 #define CFG_I2C2_OFFSET 0x3100 251 252 /* I2C RTC */ 253 #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ 254 #define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ 255 256 /* I2C W83782G HW-Monitoring IC */ 257 #define CFG_I2C_W83782G_ADDR 0x28 /* W83782G address */ 258 259 /* I2C temp sensor */ 260 /* Socrates uses Maxim's DS75, which is compatible with LM75 */ 261 #define CONFIG_DTT_LM75 1 262 #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ 263 #define CFG_DTT_MAX_TEMP 125 264 #define CFG_DTT_LOW_TEMP -55 265 #define CFG_DTT_HYSTERESIS 3 266 #define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */ 267 #define CFG_EEPROM_PAGE_WRITE_BITS 4 268 269 /* 270 * General PCI 271 * Memory space is mapped 1-1. 272 */ 273 #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 274 275 /* PCI is clocked by the external source at 33 MHz */ 276 #define CONFIG_PCI_CLK_FREQ 33000000 277 #define CFG_PCI1_MEM_BASE 0x80000000 278 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 279 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 280 #define CFG_PCI1_IO_BASE 0xE2000000 281 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 282 #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ 283 284 #if defined(CONFIG_PCI) 285 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 286 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 287 #endif /* CONFIG_PCI */ 288 289 290 #define CONFIG_NET_MULTI 1 291 #define CONFIG_MII 1 /* MII PHY management */ 292 #define CONFIG_TSEC1 1 293 #define CONFIG_TSEC1_NAME "TSEC0" 294 #define CONFIG_TSEC3 1 295 #define CONFIG_TSEC3_NAME "TSEC1" 296 #undef CONFIG_MPC85XX_FEC 297 298 #define TSEC1_PHY_ADDR 0 299 #define TSEC3_PHY_ADDR 1 300 301 #define TSEC1_PHYIDX 0 302 #define TSEC3_PHYIDX 0 303 #define TSEC1_FLAGS TSEC_GIGABIT 304 #define TSEC3_FLAGS TSEC_GIGABIT 305 306 /* Options are: TSEC[0,1] */ 307 #define CONFIG_ETHPRIME "TSEC0" 308 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 309 310 #define CONFIG_HAS_ETH0 311 #define CONFIG_HAS_ETH1 312 313 /* 314 * Environment 315 */ 316 #define CONFIG_ENV_IS_IN_FLASH 1 317 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 318 #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 319 #define CONFIG_ENV_SIZE 0x4000 320 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 321 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 322 323 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 324 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 325 326 #define CONFIG_TIMESTAMP /* Print image info with ts */ 327 328 329 /* 330 * BOOTP options 331 */ 332 #define CONFIG_BOOTP_BOOTFILESIZE 333 #define CONFIG_BOOTP_BOOTPATH 334 #define CONFIG_BOOTP_GATEWAY 335 #define CONFIG_BOOTP_HOSTNAME 336 337 338 /* 339 * Command line configuration. 340 */ 341 #include <config_cmd_default.h> 342 343 #define CONFIG_CMD_DATE 344 #define CONFIG_CMD_DHCP 345 #define CONFIG_CMD_DTT 346 #undef CONFIG_CMD_EEPROM 347 #define CONFIG_CMD_I2C 348 #define CONFIG_CMD_SDRAM 349 #define CONFIG_CMD_MII 350 #define CONFIG_CMD_NFS 351 #define CONFIG_CMD_PING 352 #define CONFIG_CMD_SNTP 353 #define CONFIG_CMD_USB 354 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 355 #define CONFIG_CMD_BMP 356 357 #if defined(CONFIG_PCI) 358 #define CONFIG_CMD_PCI 359 #endif 360 361 #undef CONFIG_WATCHDOG /* watchdog disabled */ 362 363 /* 364 * Miscellaneous configurable options 365 */ 366 #define CFG_LONGHELP /* undef to save memory */ 367 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 368 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 369 370 #if defined(CONFIG_CMD_KGDB) 371 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 372 #else 373 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 374 #endif 375 376 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ 377 #define CFG_MAXARGS 16 /* max number of command args */ 378 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 379 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 380 381 /* 382 * For booting Linux, the board info and command line data 383 * have to be in the first 8 MB of memory, since this is 384 * the maximum mapped by the Linux kernel during initialization. 385 */ 386 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 387 388 /* 389 * Internal Definitions 390 * 391 * Boot Flags 392 */ 393 #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ 394 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 395 396 #if defined(CONFIG_CMD_KGDB) 397 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ 398 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 399 #endif 400 401 402 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ 403 404 #define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */ 405 406 #define CONFIG_PREBOOT "echo;" \ 407 "echo Welcome on the ABB Socrates Board;" \ 408 "echo" 409 410 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 411 412 #define CONFIG_EXTRA_ENV_SETTINGS \ 413 "netdev=eth0\0" \ 414 "consdev=ttyS0\0" \ 415 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ 416 "bootfile=/home/tftp/syscon3/uImage\0" \ 417 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ 418 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ 419 "uboot_addr=FFFA0000\0" \ 420 "kernel_addr=FE000000\0" \ 421 "fdt_addr=FE1E0000\0" \ 422 "ramdisk_addr=FE200000\0" \ 423 "fdt_addr_r=B00000\0" \ 424 "kernel_addr_r=200000\0" \ 425 "ramdisk_addr_r=400000\0" \ 426 "rootpath=/opt/eldk/ppc_85xxDP\0" \ 427 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 428 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 429 "nfsroot=$serverip:$rootpath\0" \ 430 "addcons=setenv bootargs $bootargs " \ 431 "console=$consdev,$baudrate\0" \ 432 "addip=setenv bootargs $bootargs " \ 433 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ 434 ":$hostname:$netdev:off panic=1\0" \ 435 "boot_nor=run ramargs addcons;" \ 436 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 437 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 438 "tftp ${fdt_addr_r} ${fdt_file}; " \ 439 "run nfsargs addip addcons;" \ 440 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 441 "update_uboot=tftp 100000 ${uboot_file};" \ 442 "protect off fffa0000 ffffffff;" \ 443 "era fffa0000 ffffffff;" \ 444 "cp.b 100000 fffa0000 ${filesize};" \ 445 "setenv filesize;saveenv\0" \ 446 "update_kernel=tftp 100000 ${bootfile};" \ 447 "era fe000000 fe1dffff;" \ 448 "cp.b 100000 fe000000 ${filesize};" \ 449 "setenv filesize;saveenv\0" \ 450 "update_fdt=tftp 100000 ${fdt_file};" \ 451 "era fe1e0000 fe1fffff;" \ 452 "cp.b 100000 fe1e0000 ${filesize};" \ 453 "setenv filesize;saveenv\0" \ 454 "update_initrd=tftp 100000 ${initrd_file};" \ 455 "era fe200000 fe9fffff;" \ 456 "cp.b 100000 fe200000 ${filesize};" \ 457 "setenv filesize;saveenv\0" \ 458 "clean_data=era fea00000 fff5ffff\0" \ 459 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ 460 "load_usb=usb start;" \ 461 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ 462 "boot_usb=run load_usb usbargs addcons;" \ 463 "bootm ${kernel_addr_r} - ${fdt_addr};" \ 464 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 465 "" 466 #define CONFIG_BOOTCOMMAND "run boot_nor" 467 468 /* pass open firmware flat tree */ 469 #define CONFIG_OF_LIBFDT 1 470 #define CONFIG_OF_BOARD_SETUP 1 471 472 /* USB support */ 473 #define CONFIG_USB_OHCI_NEW 1 474 #define CONFIG_PCI_OHCI 1 475 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ 476 #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) 477 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 478 #define CFG_USB_OHCI_SLOT_NAME "ohci_pci" 479 #define CFG_OHCI_SWAP_REG_ACCESS 1 480 #define CONFIG_DOS_PARTITION 1 481 #define CONFIG_USB_STORAGE 1 482 483 #endif /* __CONFIG_H */ 484