1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * Wolfgang Denk <wd@denx.de> 6 * Copyright 2004 Freescale Semiconductor. 7 * (C) Copyright 2002,2003 Motorola,Inc. 8 * Xianghua Xiao <X.Xiao@motorola.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 /* 30 * Socrates 31 */ 32 33 #ifndef __CONFIG_H 34 #define __CONFIG_H 35 36 /* High Level Configuration Options */ 37 #define CONFIG_BOOKE 1 /* BOOKE */ 38 #define CONFIG_E500 1 /* BOOKE e500 family */ 39 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 40 #define CONFIG_MPC8544 1 41 #define CONFIG_SOCRATES 1 42 43 #define CONFIG_PCI 44 45 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 46 47 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ 48 49 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 50 51 /* 52 * Only possible on E500 Version 2 or newer cores. 53 */ 54 #define CONFIG_ENABLE_36BIT_PHYS 1 55 56 /* 57 * sysclk for MPC85xx 58 * 59 * Two valid values are: 60 * 33000000 61 * 66000000 62 * 63 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 64 * is likely the desired value here, so that is now the default. 65 * The board, however, can run at 66MHz. In any event, this value 66 * must match the settings of some switches. Details can be found 67 * in the README.mpc85xxads. 68 */ 69 70 #ifndef CONFIG_SYS_CLK_FREQ 71 #define CONFIG_SYS_CLK_FREQ 66666666 72 #endif 73 74 /* 75 * These can be toggled for performance analysis, otherwise use default. 76 */ 77 #define CONFIG_L2_CACHE /* toggle L2 cache */ 78 #define CONFIG_BTB /* toggle branch predition */ 79 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 80 81 #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 82 83 #undef CFG_DRAM_TEST /* memory test, takes time */ 84 #define CFG_MEMTEST_START 0x00000000 85 #define CFG_MEMTEST_END 0x10000000 86 87 /* 88 * Base addresses -- Note these are effective addresses where the 89 * actual resources get mapped (not physical addresses) 90 */ 91 #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ 92 #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ 93 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 94 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 95 96 /* 97 * DDR Setup 98 */ 99 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ 100 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 101 102 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ 103 104 /* Hardcoded values, to use instead of SPD */ 105 #define CFG_DDR_CS0_BNDS 0x0000000f 106 #define CFG_DDR_CS0_CONFIG 0x80010102 107 #define CFG_DDR_TIMING_0 0x00260802 108 #define CFG_DDR_TIMING_1 0x3935D322 109 #define CFG_DDR_TIMING_2 0x14904CC8 110 #define CFG_DDR_MODE 0x00480432 111 #define CFG_DDR_INTERVAL 0x030C0100 112 #define CFG_DDR_CONFIG_2 0x04400000 113 #define CFG_DDR_CONFIG 0xC3008000 114 #define CFG_DDR_CLK_CONTROL 0x03800000 115 #define CFG_SDRAM_SIZE 256 /* in Megs */ 116 117 #if 1 118 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ 119 #define SPD_EEPROM_ADDRESS 0x50 /* DDR DIMM */ 120 #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ 121 #endif 122 123 /* 124 * Flash on the Local Bus 125 */ 126 /* 127 * Flash on the LocalBus 128 */ 129 #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 130 131 #define CFG_FLASH0 0xFE000000 132 #define CFG_FLASH1 0xFC000000 133 #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } 134 135 #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ 136 #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ 137 138 #define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */ 139 #define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */ 140 #define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */ 141 #define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */ 142 143 #define CFG_FLASH_CFI /* flash is CFI compat. */ 144 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ 145 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ 146 147 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 148 #define CFG_MAX_FLASH_SECT 512 /* sectors per device */ 149 #undef CFG_FLASH_CHECKSUM 150 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 151 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 152 153 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 154 155 #define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ 156 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ 157 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 158 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ 159 160 #define CONFIG_L1_INIT_RAM 161 #define CFG_INIT_RAM_LOCK 1 162 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 163 #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ 164 165 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ 166 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 167 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 168 169 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ 170 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 171 172 /* Serial Port */ 173 174 #define CONFIG_CONS_INDEX 1 175 #undef CONFIG_SERIAL_SOFTWARE_FIFO 176 #define CFG_NS16550 177 #define CFG_NS16550_SERIAL 178 #define CFG_NS16550_REG_SIZE 1 179 #define CFG_NS16550_CLK get_bus_freq(0) 180 181 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 182 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 183 184 #define CONFIG_BAUDRATE 115200 185 186 #define CFG_BAUDRATE_TABLE \ 187 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 188 189 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 190 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ 191 #ifdef CFG_HUSH_PARSER 192 #define CFG_PROMPT_HUSH_PS2 "> " 193 #endif 194 195 196 /* 197 * I2C 198 */ 199 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 200 #define CONFIG_HARD_I2C /* I2C with hardware support */ 201 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 202 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 203 #define CFG_I2C_SLAVE 0x7F 204 #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ 205 #define CFG_I2C_OFFSET 0x3000 206 207 /* I2C RTC */ 208 #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ 209 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 210 211 #if 0 212 /* I2C EEPROM */ 213 /* 214 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also). 215 */ 216 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 217 #define CFG_I2C_EEPROM_ADDR_LEN 2 218 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ 219 #define CFG_EEPROM_PAGE_WRITE_ENABLE 220 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 221 #define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ 222 223 /* I2C SYSMON (LM75) */ 224 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 225 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 226 #define CFG_DTT_MAX_TEMP 70 227 #define CFG_DTT_LOW_TEMP -30 228 #define CFG_DTT_HYSTERESIS 3 229 #endif 230 231 /* RapidIO MMU */ 232 #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ 233 #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE 234 #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ 235 236 /* 237 * General PCI 238 * Memory space is mapped 1-1. 239 */ 240 #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 241 242 243 #define CFG_PCI1_MEM_BASE 0x80000000 244 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 245 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ 246 #define CFG_PCI1_IO_BASE 0xE2000000 247 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE 248 #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ 249 250 #if defined(CONFIG_PCI) 251 252 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 253 254 #define CONFIG_EEPRO100 255 #undef CONFIG_TULIP 256 257 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 258 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 259 260 #endif /* CONFIG_PCI */ 261 262 263 #define CONFIG_NET_MULTI 1 264 #define CONFIG_MII 1 /* MII PHY management */ 265 #define CONFIG_TSEC1 1 266 #define CONFIG_TSEC1_NAME "TSEC0" 267 #define CONFIG_TSEC2 1 268 #define CONFIG_TSEC2_NAME "TSEC1" 269 #undef CONFIG_MPC85XX_FEC 270 271 #define TSEC1_PHY_ADDR 0 272 #define TSEC2_PHY_ADDR 1 273 274 #define TSEC1_PHYIDX 0 275 #define TSEC2_PHYIDX 0 276 #define TSEC1_FLAGS TSEC_GIGABIT 277 #define TSEC2_FLAGS TSEC_GIGABIT 278 279 /* Options are: TSEC[0-1] */ 280 #define CONFIG_ETHPRIME "TSEC0" 281 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 282 283 /* 284 * Environment 285 */ 286 #define CFG_ENV_IS_IN_FLASH 1 287 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 288 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) 289 #define CFG_ENV_SIZE 0x4000 290 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) 291 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) 292 293 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 294 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 295 296 #define CONFIG_TIMESTAMP /* Print image info with ts */ 297 298 299 /* 300 * BOOTP options 301 */ 302 #define CONFIG_BOOTP_BOOTFILESIZE 303 #define CONFIG_BOOTP_BOOTPATH 304 #define CONFIG_BOOTP_GATEWAY 305 #define CONFIG_BOOTP_HOSTNAME 306 307 308 /* 309 * Command line configuration. 310 */ 311 #include <config_cmd_default.h> 312 313 #define CONFIG_CMD_DATE 314 #define CONFIG_CMD_DHCP 315 #undef CONFIG_CMD_DTT 316 #undef CONFIG_CMD_EEPROM 317 #define CONFIG_CMD_I2C 318 #define CONFIG_CMD_MII 319 #define CONFIG_CMD_NFS 320 #define CONFIG_CMD_PING 321 #undef CONFIG_CMD_RTC 322 #define CONFIG_CMD_SNTP 323 324 325 #if defined(CONFIG_PCI) 326 #define CONFIG_CMD_PCI 327 #endif 328 329 330 #undef CONFIG_WATCHDOG /* watchdog disabled */ 331 332 /* 333 * Miscellaneous configurable options 334 */ 335 #define CFG_LONGHELP /* undef to save memory */ 336 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 337 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 338 339 #if defined(CONFIG_CMD_KGDB) 340 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 341 #else 342 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 343 #endif 344 345 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ 346 #define CFG_MAXARGS 16 /* max number of command args */ 347 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 348 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 349 350 /* 351 * For booting Linux, the board info and command line data 352 * have to be in the first 8 MB of memory, since this is 353 * the maximum mapped by the Linux kernel during initialization. 354 */ 355 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 356 357 /* 358 * Internal Definitions 359 * 360 * Boot Flags 361 */ 362 #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ 363 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 364 365 #if defined(CONFIG_CMD_KGDB) 366 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ 367 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 368 #endif 369 370 371 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ 372 373 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 374 375 #define CONFIG_PREBOOT "echo;" \ 376 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 377 "echo" 378 379 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 380 381 #define CONFIG_EXTRA_ENV_SETTINGS \ 382 "bootfile=/tftpboot/socrates\0" \ 383 "netdev=eth0\0" \ 384 "consdev=ttyS0\0" \ 385 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 386 "nfsroot=$serverip:$rootpath\0" \ 387 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 388 "addip=setenv bootargs $bootargs " \ 389 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ 390 ":$hostname:$netdev:off panic=1\0" \ 391 "addcons=setenv bootargs $bootargs " \ 392 "console=$consdev,$baudrate\0" \ 393 "flash_nfs=run nfsargs addip addcons;" \ 394 "bootm $kernel_addr\0" \ 395 "flash_self=run ramargs addip addcons;" \ 396 "bootm $kernel_addr $ramdisk_addr\0" \ 397 "net_nfs=tftp $loadaddr $bootfile;" \ 398 "run nfsargs addip addcons;bootm\0" \ 399 "rootpath=/opt/eldk/ppc_85xx\0" \ 400 "kernel_addr=FE000000\0" \ 401 "ramdisk_addr=FE180000\0" \ 402 "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ 403 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ 404 "cp.b 100000 fffc0000 40000;" \ 405 "setenv filesize;saveenv\0" \ 406 "upd=run load update\0" \ 407 "" 408 #define CONFIG_BOOTCOMMAND "run flash_self" 409 410 #endif /* __CONFIG_H */ 411