1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * Wolfgang Denk <wd@denx.de> 6 * Copyright 2004 Freescale Semiconductor. 7 * (C) Copyright 2002,2003 Motorola,Inc. 8 * Xianghua Xiao <X.Xiao@motorola.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * Socrates 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* High Level Configuration Options */ 21 #define CONFIG_BOOKE 1 /* BOOKE */ 22 #define CONFIG_E500 1 /* BOOKE e500 family */ 23 #define CONFIG_MPC8544 1 24 #define CONFIG_SOCRATES 1 25 26 #define CONFIG_SYS_TEXT_BASE 0xfff80000 27 28 #define CONFIG_PCI 29 #define CONFIG_PCI_INDIRECT_BRIDGE 30 31 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 32 33 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ 34 #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ 35 36 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 37 38 /* 39 * Only possible on E500 Version 2 or newer cores. 40 */ 41 #define CONFIG_ENABLE_36BIT_PHYS 1 42 43 /* 44 * sysclk for MPC85xx 45 * 46 * Two valid values are: 47 * 33000000 48 * 66000000 49 * 50 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 51 * is likely the desired value here, so that is now the default. 52 * The board, however, can run at 66MHz. In any event, this value 53 * must match the settings of some switches. Details can be found 54 * in the README.mpc85xxads. 55 */ 56 57 #ifndef CONFIG_SYS_CLK_FREQ 58 #define CONFIG_SYS_CLK_FREQ 66666666 59 #endif 60 61 /* 62 * These can be toggled for performance analysis, otherwise use default. 63 */ 64 #define CONFIG_L2_CACHE /* toggle L2 cache */ 65 #define CONFIG_BTB /* toggle branch predition */ 66 67 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 68 69 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 70 #define CONFIG_SYS_MEMTEST_START 0x00400000 71 #define CONFIG_SYS_MEMTEST_END 0x00C00000 72 73 #define CONFIG_SYS_CCSRBAR 0xE0000000 74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 75 76 /* DDR Setup */ 77 #define CONFIG_SYS_FSL_DDR2 78 #undef CONFIG_FSL_DDR_INTERACTIVE 79 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 80 #define CONFIG_DDR_SPD 81 82 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 83 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 84 85 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 86 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 87 #define CONFIG_VERY_BIG_RAM 88 89 #define CONFIG_NUM_DDR_CONTROLLERS 1 90 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 91 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 92 93 /* I2C addresses of SPD EEPROMs */ 94 #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ 95 96 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ 97 98 /* Hardcoded values, to use instead of SPD */ 99 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 100 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 101 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 102 #define CONFIG_SYS_DDR_TIMING_1 0x3935D322 103 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 104 #define CONFIG_SYS_DDR_MODE 0x00480432 105 #define CONFIG_SYS_DDR_INTERVAL 0x030C0100 106 #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 107 #define CONFIG_SYS_DDR_CONFIG 0xC3008000 108 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 109 #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ 110 111 /* 112 * Flash on the LocalBus 113 */ 114 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 115 116 #define CONFIG_SYS_FLASH0 0xFE000000 117 #define CONFIG_SYS_FLASH1 0xFC000000 118 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } 119 120 #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ 121 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ 122 123 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ 124 #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ 125 #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ 126 #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ 127 128 #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ 129 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ 130 131 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 132 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 133 #undef CONFIG_SYS_FLASH_CHECKSUM 134 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 135 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 136 137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 138 139 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 140 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 141 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 142 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ 143 144 #define CONFIG_SYS_INIT_RAM_LOCK 1 145 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 146 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ 147 148 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 149 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 150 151 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ 152 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ 153 154 /* FPGA and NAND */ 155 #define CONFIG_SYS_FPGA_BASE 0xc0000000 156 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ 157 #define CONFIG_SYS_HMI_BASE 0xc0010000 158 #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ 159 #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ 160 161 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) 162 #define CONFIG_SYS_MAX_NAND_DEVICE 1 163 #define CONFIG_CMD_NAND 164 165 /* LIME GDC */ 166 #define CONFIG_SYS_LIME_BASE 0xc8000000 167 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ 168 #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ 169 #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ 170 171 #define CONFIG_VIDEO_MB862xx 172 #define CONFIG_VIDEO_MB862xx_ACCEL 173 #define CONFIG_VIDEO_LOGO 174 #define CONFIG_VIDEO_BMP_LOGO 175 #define CONFIG_CONSOLE_EXTRA_INFO 176 #define VIDEO_FB_16BPP_PIXEL_SWAP 177 #define VIDEO_FB_16BPP_WORD_SWAP 178 #define CONFIG_VIDEO_SW_CURSOR 179 #define CONFIG_SPLASH_SCREEN 180 #define CONFIG_VIDEO_BMP_GZIP 181 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ 182 183 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ 184 #define CONFIG_SYS_MB862xx_CCF 0x10000 185 /* SDRAM parameter */ 186 #define CONFIG_SYS_MB862xx_MMR 0x4157BA63 187 188 /* Serial Port */ 189 190 #define CONFIG_CONS_INDEX 1 191 #define CONFIG_SYS_NS16550_SERIAL 192 #define CONFIG_SYS_NS16550_REG_SIZE 1 193 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 194 195 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 196 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 197 198 #define CONFIG_BAUDRATE 115200 199 200 #define CONFIG_SYS_BAUDRATE_TABLE \ 201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 202 203 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 204 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 205 206 /* 207 * I2C 208 */ 209 #define CONFIG_SYS_I2C 210 #define CONFIG_SYS_I2C_FSL 211 #define CONFIG_SYS_FSL_I2C_SPEED 102124 212 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 213 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 214 #define CONFIG_SYS_FSL_I2C2_SPEED 102124 215 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 216 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 217 218 /* I2C RTC */ 219 #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ 220 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ 221 222 /* I2C W83782G HW-Monitoring IC */ 223 #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ 224 225 /* I2C temp sensor */ 226 /* Socrates uses Maxim's DS75, which is compatible with LM75 */ 227 #define CONFIG_DTT_LM75 1 228 #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ 229 #define CONFIG_SYS_DTT_MAX_TEMP 125 230 #define CONFIG_SYS_DTT_LOW_TEMP -55 231 #define CONFIG_SYS_DTT_HYSTERESIS 3 232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 233 234 /* 235 * General PCI 236 * Memory space is mapped 1-1. 237 */ 238 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 239 240 /* PCI is clocked by the external source at 33 MHz */ 241 #define CONFIG_PCI_CLK_FREQ 33000000 242 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 243 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 244 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 245 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 246 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 247 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 248 249 #if defined(CONFIG_PCI) 250 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 251 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 252 #endif /* CONFIG_PCI */ 253 254 #define CONFIG_MII 1 /* MII PHY management */ 255 #define CONFIG_TSEC1 1 256 #define CONFIG_TSEC1_NAME "TSEC0" 257 #define CONFIG_TSEC3 1 258 #define CONFIG_TSEC3_NAME "TSEC1" 259 #undef CONFIG_MPC85XX_FEC 260 261 #define TSEC1_PHY_ADDR 0 262 #define TSEC3_PHY_ADDR 1 263 264 #define TSEC1_PHYIDX 0 265 #define TSEC3_PHYIDX 0 266 #define TSEC1_FLAGS TSEC_GIGABIT 267 #define TSEC3_FLAGS TSEC_GIGABIT 268 269 /* Options are: TSEC[0,1] */ 270 #define CONFIG_ETHPRIME "TSEC0" 271 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 272 273 #define CONFIG_HAS_ETH0 274 #define CONFIG_HAS_ETH1 275 276 /* 277 * Environment 278 */ 279 #define CONFIG_ENV_IS_IN_FLASH 1 280 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 281 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 282 #define CONFIG_ENV_SIZE 0x4000 283 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 284 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 285 286 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 287 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 288 289 #define CONFIG_TIMESTAMP /* Print image info with ts */ 290 291 /* 292 * BOOTP options 293 */ 294 #define CONFIG_BOOTP_BOOTFILESIZE 295 #define CONFIG_BOOTP_BOOTPATH 296 #define CONFIG_BOOTP_GATEWAY 297 #define CONFIG_BOOTP_HOSTNAME 298 299 /* 300 * Command line configuration. 301 */ 302 #define CONFIG_CMD_BMP 303 #define CONFIG_CMD_DATE 304 #define CONFIG_CMD_DTT 305 #undef CONFIG_CMD_EEPROM 306 #define CONFIG_CMD_SDRAM 307 #define CONFIG_CMD_REGINFO 308 309 #if defined(CONFIG_PCI) 310 #define CONFIG_CMD_PCI 311 #endif 312 313 #undef CONFIG_WATCHDOG /* watchdog disabled */ 314 315 /* 316 * Miscellaneous configurable options 317 */ 318 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 319 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 320 321 #if defined(CONFIG_CMD_KGDB) 322 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 323 #else 324 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 325 #endif 326 327 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */ 328 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 329 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 330 331 /* 332 * For booting Linux, the board info and command line data 333 * have to be in the first 8 MB of memory, since this is 334 * the maximum mapped by the Linux kernel during initialization. 335 */ 336 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 337 338 #if defined(CONFIG_CMD_KGDB) 339 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ 340 #endif 341 342 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ 343 344 345 #define CONFIG_PREBOOT "echo;" \ 346 "echo Welcome on the ABB Socrates Board;" \ 347 "echo" 348 349 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 350 351 #define CONFIG_EXTRA_ENV_SETTINGS \ 352 "netdev=eth0\0" \ 353 "consdev=ttyS0\0" \ 354 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ 355 "bootfile=/home/tftp/syscon3/uImage\0" \ 356 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ 357 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ 358 "uboot_addr=FFFA0000\0" \ 359 "kernel_addr=FE000000\0" \ 360 "fdt_addr=FE1E0000\0" \ 361 "ramdisk_addr=FE200000\0" \ 362 "fdt_addr_r=B00000\0" \ 363 "kernel_addr_r=200000\0" \ 364 "ramdisk_addr_r=400000\0" \ 365 "rootpath=/opt/eldk/ppc_85xxDP\0" \ 366 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 367 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 368 "nfsroot=$serverip:$rootpath\0" \ 369 "addcons=setenv bootargs $bootargs " \ 370 "console=$consdev,$baudrate\0" \ 371 "addip=setenv bootargs $bootargs " \ 372 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ 373 ":$hostname:$netdev:off panic=1\0" \ 374 "boot_nor=run ramargs addcons;" \ 375 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 376 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 377 "tftp ${fdt_addr_r} ${fdt_file}; " \ 378 "run nfsargs addip addcons;" \ 379 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 380 "update_uboot=tftp 100000 ${uboot_file};" \ 381 "protect off fffa0000 ffffffff;" \ 382 "era fffa0000 ffffffff;" \ 383 "cp.b 100000 fffa0000 ${filesize};" \ 384 "setenv filesize;saveenv\0" \ 385 "update_kernel=tftp 100000 ${bootfile};" \ 386 "era fe000000 fe1dffff;" \ 387 "cp.b 100000 fe000000 ${filesize};" \ 388 "setenv filesize;saveenv\0" \ 389 "update_fdt=tftp 100000 ${fdt_file};" \ 390 "era fe1e0000 fe1fffff;" \ 391 "cp.b 100000 fe1e0000 ${filesize};" \ 392 "setenv filesize;saveenv\0" \ 393 "update_initrd=tftp 100000 ${initrd_file};" \ 394 "era fe200000 fe9fffff;" \ 395 "cp.b 100000 fe200000 ${filesize};" \ 396 "setenv filesize;saveenv\0" \ 397 "clean_data=era fea00000 fff5ffff\0" \ 398 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ 399 "load_usb=usb start;" \ 400 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ 401 "boot_usb=run load_usb usbargs addcons;" \ 402 "bootm ${kernel_addr_r} - ${fdt_addr};" \ 403 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 404 "" 405 #define CONFIG_BOOTCOMMAND "run boot_nor" 406 407 /* pass open firmware flat tree */ 408 409 /* USB support */ 410 #define CONFIG_USB_OHCI_NEW 1 411 #define CONFIG_PCI_OHCI 1 412 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ 413 #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) 414 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 415 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 416 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 417 #define CONFIG_DOS_PARTITION 1 418 419 #endif /* __CONFIG_H */ 420