1 /* 2 * Copyright (C) 2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_SR1500_H__ 7 #define __CONFIG_SOCFPGA_SR1500_H__ 8 9 #include <asm/arch/base_addr_ac5.h> 10 11 #define CONFIG_BOARD_EARLY_INIT_F 12 13 #define CONFIG_SYS_NO_FLASH 14 #define CONFIG_DOS_PARTITION 15 #define CONFIG_FAT_WRITE 16 17 #define CONFIG_HW_WATCHDOG 18 19 /* U-Boot Commands */ 20 #define CONFIG_CMD_ASKENV 21 #define CONFIG_CMD_BOOTZ 22 #define CONFIG_CMD_CACHE 23 #define CONFIG_CMD_EXT4 24 #define CONFIG_CMD_EXT4_WRITE 25 #define CONFIG_CMD_FAT 26 #define CONFIG_CMD_FS_GENERIC 27 #define CONFIG_CMD_GREPENV 28 #define CONFIG_CMD_MII 29 #define CONFIG_CMD_MMC 30 31 /* Memory configurations */ 32 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ 33 34 /* Booting Linux */ 35 #define CONFIG_BOOTDELAY 3 36 #define CONFIG_BOOTFILE "uImage" 37 #define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) 38 #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" 39 #define CONFIG_LOADADDR 0x01000000 40 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 41 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 42 43 /* Ethernet on SoC (EMAC) */ 44 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII 45 /* The PHY is autodetected, so no MII PHY address is needed here */ 46 #define CONFIG_PHY_MARVELL 47 #define PHY_ANEG_TIMEOUT 8000 48 49 #define CONFIG_EXTRA_ENV_SETTINGS \ 50 "verify=n\0" \ 51 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 52 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ 53 "bootm ${loadaddr} - ${fdt_addr}\0" \ 54 "bootimage=zImage\0" \ 55 "fdt_addr=100\0" \ 56 "fdtimage=socfpga.dtb\0" \ 57 "fsloadcmd=ext2load\0" \ 58 "bootm ${loadaddr} - ${fdt_addr}\0" \ 59 "mmcroot=/dev/mmcblk0p2\0" \ 60 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ 61 " root=${mmcroot} rw rootwait;" \ 62 "bootz ${loadaddr} - ${fdt_addr}\0" \ 63 "mmcload=mmc rescan;" \ 64 "load mmc 0:1 ${loadaddr} ${bootimage};" \ 65 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ 66 "qspiload=sf probe && mtdparts default && run ubiload\0" \ 67 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ 68 " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ 69 "bootz ${loadaddr} - ${fdt_addr}\0" \ 70 "ubiload=ubi part UBI && ubifsmount ubi0 && " \ 71 "ubifsload ${loadaddr} /boot/${bootimage} && " \ 72 "ubifsload ${fdt_addr} /boot/${fdtimage}\0" 73 74 /* Environment */ 75 #define CONFIG_ENV_IS_IN_SPI_FLASH 76 77 /* Enable SPI NOR flash reset, needed for SPI booting */ 78 #define CONFIG_SPI_N25Q256A_RESET 79 80 /* 81 * Bootcounter 82 */ 83 #define CONFIG_BOOTCOUNT_LIMIT 84 /* last 2 lwords in OCRAM */ 85 #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 86 #define CONFIG_SYS_BOOTCOUNT_BE 87 88 /* Environment setting for SPI flash */ 89 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 90 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 91 #define CONFIG_ENV_SIZE (16 * 1024) 92 #define CONFIG_ENV_OFFSET 0x000e0000 93 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 94 #define CONFIG_ENV_SPI_BUS 0 95 #define CONFIG_ENV_SPI_CS 0 96 #define CONFIG_ENV_SPI_MODE SPI_MODE_3 97 #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */ 98 #define CONFIG_SF_DEFAULT_SPEED 100000000 99 100 /* 101 * The QSPI NOR flash layout on SR1500: 102 * 103 * 0000.0000 - 0003.ffff: SPL (4 times) 104 * 0004.0000 - 000d.ffff: U-Boot 105 * 000e.0000 - 000e.ffff: env1 106 * 000f.0000 - 000f.ffff: env2 107 */ 108 109 /* The rest of the configuration is shared */ 110 #include <configs/socfpga_common.h> 111 112 #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ 113