1ae9996c8SStefan Roese /* 2ae9996c8SStefan Roese * Copyright (C) 2015 Stefan Roese <sr@denx.de> 3ae9996c8SStefan Roese * 4ae9996c8SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5ae9996c8SStefan Roese */ 6ae9996c8SStefan Roese #ifndef __CONFIG_SOCFPGA_SR1500_H__ 7ae9996c8SStefan Roese #define __CONFIG_SOCFPGA_SR1500_H__ 8ae9996c8SStefan Roese 9ae9996c8SStefan Roese #include <asm/arch/base_addr_ac5.h> 10ae9996c8SStefan Roese 11ae9996c8SStefan Roese #define CONFIG_BOARD_EARLY_INIT_F 12ae9996c8SStefan Roese 13ae9996c8SStefan Roese #define CONFIG_SYS_NO_FLASH 14ae9996c8SStefan Roese #define CONFIG_DOS_PARTITION 15ae9996c8SStefan Roese #define CONFIG_FAT_WRITE 16ae9996c8SStefan Roese 17ae9996c8SStefan Roese #define CONFIG_HW_WATCHDOG 18ae9996c8SStefan Roese 19ae9996c8SStefan Roese /* U-Boot Commands */ 20ae9996c8SStefan Roese #define CONFIG_CMD_ASKENV 21ae9996c8SStefan Roese #define CONFIG_CMD_BOOTZ 22ae9996c8SStefan Roese #define CONFIG_CMD_CACHE 23ae9996c8SStefan Roese #define CONFIG_CMD_DHCP 24ae9996c8SStefan Roese #define CONFIG_CMD_EXT4 25ae9996c8SStefan Roese #define CONFIG_CMD_EXT4_WRITE 26ae9996c8SStefan Roese #define CONFIG_CMD_FAT 27ae9996c8SStefan Roese #define CONFIG_CMD_FS_GENERIC 28ae9996c8SStefan Roese #define CONFIG_CMD_GPIO 29ae9996c8SStefan Roese #define CONFIG_CMD_GREPENV 30ae9996c8SStefan Roese #define CONFIG_CMD_MEMTEST 31ae9996c8SStefan Roese #define CONFIG_CMD_MII 32ae9996c8SStefan Roese #define CONFIG_CMD_MMC 33ae9996c8SStefan Roese #define CONFIG_CMD_PING 34ae9996c8SStefan Roese #define CONFIG_CMD_SF 35ae9996c8SStefan Roese #define CONFIG_CMD_SPI 36ae9996c8SStefan Roese #define CONFIG_CMD_TIME 37ae9996c8SStefan Roese 38ae9996c8SStefan Roese /* Memory configurations */ 39ae9996c8SStefan Roese #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ 40ae9996c8SStefan Roese 41ae9996c8SStefan Roese /* Booting Linux */ 42ae9996c8SStefan Roese #define CONFIG_BOOTDELAY 3 43ae9996c8SStefan Roese #define CONFIG_BOOTFILE "uImage" 44ae9996c8SStefan Roese #define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) 45ae9996c8SStefan Roese #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" 46ae9996c8SStefan Roese #define CONFIG_LOADADDR 0x01000000 47ae9996c8SStefan Roese #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 48ae9996c8SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 49ae9996c8SStefan Roese 50ae9996c8SStefan Roese /* Ethernet on SoC (EMAC) */ 51ae9996c8SStefan Roese #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII 52ae9996c8SStefan Roese /* The PHY is autodetected, so no MII PHY address is needed here */ 53ae9996c8SStefan Roese #define CONFIG_PHY_MARVELL 54ae9996c8SStefan Roese #define PHY_ANEG_TIMEOUT 8000 55ae9996c8SStefan Roese 56ae9996c8SStefan Roese #define CONFIG_EXTRA_ENV_SETTINGS \ 57ae9996c8SStefan Roese "verify=n\0" \ 58ae9996c8SStefan Roese "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 59ae9996c8SStefan Roese "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ 60ae9996c8SStefan Roese "bootm ${loadaddr} - ${fdt_addr}\0" \ 61ae9996c8SStefan Roese "bootimage=zImage\0" \ 62ae9996c8SStefan Roese "fdt_addr=100\0" \ 63ae9996c8SStefan Roese "fdtimage=socfpga.dtb\0" \ 64ae9996c8SStefan Roese "fsloadcmd=ext2load\0" \ 65ae9996c8SStefan Roese "bootm ${loadaddr} - ${fdt_addr}\0" \ 66ae9996c8SStefan Roese "mmcroot=/dev/mmcblk0p2\0" \ 67ae9996c8SStefan Roese "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ 68ae9996c8SStefan Roese " root=${mmcroot} rw rootwait;" \ 69ae9996c8SStefan Roese "bootz ${loadaddr} - ${fdt_addr}\0" \ 70ae9996c8SStefan Roese "mmcload=mmc rescan;" \ 71ae9996c8SStefan Roese "load mmc 0:1 ${loadaddr} ${bootimage};" \ 72ae9996c8SStefan Roese "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ 73b3bb1110SChin Liang See "qspiload=sf probe && mtdparts default && run ubiload\0" \ 74ae9996c8SStefan Roese "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ 7594f53a7dSChin Liang See " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ 7694f53a7dSChin Liang See "bootz ${loadaddr} - ${fdt_addr}\0" \ 77eb45022cSChin Liang See "ubiload=ubi part UBI && ubifsmount ubi0 && " \ 78eb45022cSChin Liang See "ubifsload ${loadaddr} /boot/${bootimage} && " \ 79eb45022cSChin Liang See "ubifsload ${fdt_addr} /boot/${fdtimage}\0" 80ae9996c8SStefan Roese 81ae9996c8SStefan Roese /* Environment */ 82ae9996c8SStefan Roese #define CONFIG_ENV_IS_IN_SPI_FLASH 83ae9996c8SStefan Roese 84ae9996c8SStefan Roese /* Enable SPI NOR flash reset, needed for SPI booting */ 85ae9996c8SStefan Roese #define CONFIG_SPI_N25Q256A_RESET 86ae9996c8SStefan Roese 87ae9996c8SStefan Roese /* 88ae9996c8SStefan Roese * Bootcounter 89ae9996c8SStefan Roese */ 90ae9996c8SStefan Roese #define CONFIG_BOOTCOUNT_LIMIT 91ae9996c8SStefan Roese /* last 2 lwords in OCRAM */ 92ae9996c8SStefan Roese #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 93ae9996c8SStefan Roese #define CONFIG_SYS_BOOTCOUNT_BE 94ae9996c8SStefan Roese 95ae9996c8SStefan Roese /* Environment setting for SPI flash */ 96ae9996c8SStefan Roese #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 97ae9996c8SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 * 1024) 98ae9996c8SStefan Roese #define CONFIG_ENV_SIZE (16 * 1024) 99*93d9fc26SStefan Roese #define CONFIG_ENV_OFFSET 0x000e0000 100ae9996c8SStefan Roese #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 101ae9996c8SStefan Roese #define CONFIG_ENV_SPI_BUS 0 102ae9996c8SStefan Roese #define CONFIG_ENV_SPI_CS 0 103ae9996c8SStefan Roese #define CONFIG_ENV_SPI_MODE SPI_MODE_3 104*93d9fc26SStefan Roese #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */ 105*93d9fc26SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 100000000 106*93d9fc26SStefan Roese 107*93d9fc26SStefan Roese /* 108*93d9fc26SStefan Roese * The QSPI NOR flash layout on SR1500: 109*93d9fc26SStefan Roese * 110*93d9fc26SStefan Roese * 0000.0000 - 0003.ffff: SPL (4 times) 111*93d9fc26SStefan Roese * 0004.0000 - 000d.ffff: U-Boot 112*93d9fc26SStefan Roese * 000e.0000 - 000e.ffff: env1 113*93d9fc26SStefan Roese * 000f.0000 - 000f.ffff: env2 114*93d9fc26SStefan Roese */ 115ae9996c8SStefan Roese 116b72041ccSMarek Vasut /* The rest of the configuration is shared */ 117b72041ccSMarek Vasut #include <configs/socfpga_common.h> 118b72041ccSMarek Vasut 119ae9996c8SStefan Roese #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ 120