1ae9996c8SStefan Roese /* 2ae9996c8SStefan Roese * Copyright (C) 2015 Stefan Roese <sr@denx.de> 3ae9996c8SStefan Roese * 4ae9996c8SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5ae9996c8SStefan Roese */ 6ae9996c8SStefan Roese #ifndef __CONFIG_SOCFPGA_SR1500_H__ 7ae9996c8SStefan Roese #define __CONFIG_SOCFPGA_SR1500_H__ 8ae9996c8SStefan Roese 9ae9996c8SStefan Roese #include <asm/arch/base_addr_ac5.h> 10ae9996c8SStefan Roese 11ae9996c8SStefan Roese #define CONFIG_HW_WATCHDOG 12ae9996c8SStefan Roese 13ae9996c8SStefan Roese /* Memory configurations */ 14ae9996c8SStefan Roese #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ 15ae9996c8SStefan Roese 16ae9996c8SStefan Roese /* Booting Linux */ 17ae9996c8SStefan Roese #define CONFIG_LOADADDR 0x01000000 18ae9996c8SStefan Roese #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 19ae9996c8SStefan Roese 20ae9996c8SStefan Roese /* Ethernet on SoC (EMAC) */ 21ae9996c8SStefan Roese #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII 22ae9996c8SStefan Roese /* The PHY is autodetected, so no MII PHY address is needed here */ 23ae9996c8SStefan Roese #define CONFIG_PHY_MARVELL 24ae9996c8SStefan Roese #define PHY_ANEG_TIMEOUT 8000 25ae9996c8SStefan Roese 26ae9996c8SStefan Roese /* Environment */ 27ae9996c8SStefan Roese 28ae9996c8SStefan Roese /* Enable SPI NOR flash reset, needed for SPI booting */ 29ae9996c8SStefan Roese #define CONFIG_SPI_N25Q256A_RESET 30ae9996c8SStefan Roese 31ae9996c8SStefan Roese /* 32ae9996c8SStefan Roese * Bootcounter 33ae9996c8SStefan Roese */ 34ae9996c8SStefan Roese #define CONFIG_BOOTCOUNT_LIMIT 35ae9996c8SStefan Roese /* last 2 lwords in OCRAM */ 36ae9996c8SStefan Roese #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 37ae9996c8SStefan Roese #define CONFIG_SYS_BOOTCOUNT_BE 38ae9996c8SStefan Roese 39ae9996c8SStefan Roese /* Environment setting for SPI flash */ 40ae9996c8SStefan Roese #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 41ae9996c8SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 * 1024) 42ae9996c8SStefan Roese #define CONFIG_ENV_SIZE (16 * 1024) 43*93d9fc26SStefan Roese #define CONFIG_ENV_OFFSET 0x000e0000 44ae9996c8SStefan Roese #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 45ae9996c8SStefan Roese #define CONFIG_ENV_SPI_BUS 0 46ae9996c8SStefan Roese #define CONFIG_ENV_SPI_CS 0 47ae9996c8SStefan Roese #define CONFIG_ENV_SPI_MODE SPI_MODE_3 48*93d9fc26SStefan Roese #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */ 49*93d9fc26SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 100000000 50*93d9fc26SStefan Roese 51*93d9fc26SStefan Roese /* 52*93d9fc26SStefan Roese * The QSPI NOR flash layout on SR1500: 53*93d9fc26SStefan Roese * 54*93d9fc26SStefan Roese * 0000.0000 - 0003.ffff: SPL (4 times) 55*93d9fc26SStefan Roese * 0004.0000 - 000d.ffff: U-Boot 56*93d9fc26SStefan Roese * 000e.0000 - 000e.ffff: env1 57*93d9fc26SStefan Roese * 000f.0000 - 000f.ffff: env2 58*93d9fc26SStefan Roese */ 59ae9996c8SStefan Roese 60b72041ccSMarek Vasut /* The rest of the configuration is shared */ 61b72041ccSMarek Vasut #include <configs/socfpga_common.h> 62b72041ccSMarek Vasut 63ae9996c8SStefan Roese #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ 64