1*6bd041f0SDalon Westergreen /* 2*6bd041f0SDalon Westergreen * Copyright (C) 2017, Intel Corporation 3*6bd041f0SDalon Westergreen * 4*6bd041f0SDalon Westergreen * SPDX-License-Identifier: GPL-2.0+ 5*6bd041f0SDalon Westergreen */ 6*6bd041f0SDalon Westergreen #ifndef __CONFIG_TERASIC_DE10_H__ 7*6bd041f0SDalon Westergreen #define __CONFIG_TERASIC_DE10_H__ 8*6bd041f0SDalon Westergreen 9*6bd041f0SDalon Westergreen #include <asm/arch/base_addr_ac5.h> 10*6bd041f0SDalon Westergreen 11*6bd041f0SDalon Westergreen #define CONFIG_HW_WATCHDOG 12*6bd041f0SDalon Westergreen 13*6bd041f0SDalon Westergreen /* Memory configurations */ 14*6bd041f0SDalon Westergreen #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ 15*6bd041f0SDalon Westergreen 16*6bd041f0SDalon Westergreen /* Booting Linux */ 17*6bd041f0SDalon Westergreen #define CONFIG_LOADADDR 0x01000000 18*6bd041f0SDalon Westergreen #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 19*6bd041f0SDalon Westergreen 20*6bd041f0SDalon Westergreen /* Ethernet on SoC (EMAC) */ 21*6bd041f0SDalon Westergreen 22*6bd041f0SDalon Westergreen /* The rest of the configuration is shared */ 23*6bd041f0SDalon Westergreen #include <configs/socfpga_common.h> 24*6bd041f0SDalon Westergreen 25*6bd041f0SDalon Westergreen #endif /* __CONFIG_TERASIC_DE10_H__ */ 26