1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 /* Virtual target or real hardware */ 10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12 /* 13 * High level configuration 14 */ 15 #define CONFIG_DISPLAY_BOARDINFO_LATE 16 #define CONFIG_CLOCKS 17 18 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 19 20 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 21 22 /* add target to build it automatically upon "make" */ 23 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 24 25 /* 26 * Memory configurations 27 */ 28 #define CONFIG_NR_DRAM_BANKS 1 29 #define PHYS_SDRAM_1 0x0 30 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 31 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 32 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 33 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 34 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 35 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 36 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 37 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 38 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 39 #endif 40 #define CONFIG_SYS_INIT_SP_OFFSET \ 41 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 42 #define CONFIG_SYS_INIT_SP_ADDR \ 43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 44 45 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 46 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 47 #define CONFIG_SYS_TEXT_BASE 0x08000040 48 #else 49 #define CONFIG_SYS_TEXT_BASE 0x01000040 50 #endif 51 52 /* 53 * U-Boot general configurations 54 */ 55 #define CONFIG_SYS_LONGHELP 56 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 57 #define CONFIG_SYS_PBSIZE \ 58 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 59 /* Print buffer size */ 60 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 61 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 62 /* Boot argument buffer size */ 63 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 64 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 65 66 #ifndef CONFIG_SYS_HOSTNAME 67 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 68 #endif 69 70 #define CONFIG_CMD_PXE 71 #define CONFIG_MENU 72 73 /* 74 * Cache 75 */ 76 #define CONFIG_SYS_L2_PL310 77 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 78 79 /* 80 * EPCS/EPCQx1 Serial Flash Controller 81 */ 82 #ifdef CONFIG_ALTERA_SPI 83 #define CONFIG_SF_DEFAULT_SPEED 30000000 84 /* 85 * The base address is configurable in QSys, each board must specify the 86 * base address based on it's particular FPGA configuration. Please note 87 * that the address here is incremented by 0x400 from the Base address 88 * selected in QSys, since the SPI registers are at offset +0x400. 89 * #define CONFIG_SYS_SPI_BASE 0xff240400 90 */ 91 #endif 92 93 /* 94 * Ethernet on SoC (EMAC) 95 */ 96 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 97 #define CONFIG_DW_ALTDESCRIPTOR 98 #define CONFIG_MII 99 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 100 #define CONFIG_PHY_GIGE 101 #endif 102 103 /* 104 * FPGA Driver 105 */ 106 #ifdef CONFIG_TARGET_SOCFPGA_GEN5 107 #ifdef CONFIG_CMD_FPGA 108 #define CONFIG_FPGA_COUNT 1 109 #endif 110 #endif 111 /* 112 * L4 OSC1 Timer 0 113 */ 114 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 115 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 116 #define CONFIG_SYS_TIMER_COUNTS_DOWN 117 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 118 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 119 #define CONFIG_SYS_TIMER_RATE 2400000 120 #else 121 #define CONFIG_SYS_TIMER_RATE 25000000 122 #endif 123 124 /* 125 * L4 Watchdog 126 */ 127 #ifdef CONFIG_HW_WATCHDOG 128 #define CONFIG_DESIGNWARE_WATCHDOG 129 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 130 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 131 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 132 #endif 133 134 /* 135 * MMC Driver 136 */ 137 #ifdef CONFIG_CMD_MMC 138 #define CONFIG_BOUNCE_BUFFER 139 /* FIXME */ 140 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 141 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 142 #endif 143 144 /* 145 * NAND Support 146 */ 147 #ifdef CONFIG_NAND_DENALI 148 #define CONFIG_SYS_MAX_NAND_DEVICE 1 149 #define CONFIG_SYS_NAND_MAX_CHIPS 1 150 #define CONFIG_SYS_NAND_ONFI_DETECTION 151 #define CONFIG_NAND_DENALI_ECC_SIZE 512 152 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 153 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 154 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 155 #endif 156 157 /* 158 * I2C support 159 */ 160 #define CONFIG_SYS_I2C 161 #define CONFIG_SYS_I2C_BUS_MAX 4 162 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 163 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 164 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 165 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 166 /* Using standard mode which the speed up to 100Kb/s */ 167 #define CONFIG_SYS_I2C_SPEED 100000 168 #define CONFIG_SYS_I2C_SPEED1 100000 169 #define CONFIG_SYS_I2C_SPEED2 100000 170 #define CONFIG_SYS_I2C_SPEED3 100000 171 /* Address of device when used as slave */ 172 #define CONFIG_SYS_I2C_SLAVE 0x02 173 #define CONFIG_SYS_I2C_SLAVE1 0x02 174 #define CONFIG_SYS_I2C_SLAVE2 0x02 175 #define CONFIG_SYS_I2C_SLAVE3 0x02 176 #ifndef __ASSEMBLY__ 177 /* Clock supplied to I2C controller in unit of MHz */ 178 unsigned int cm_get_l4_sp_clk_hz(void); 179 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 180 #endif 181 182 /* 183 * QSPI support 184 */ 185 /* Enable multiple SPI NOR flash manufacturers */ 186 #ifndef CONFIG_SPL_BUILD 187 #define CONFIG_SPI_FLASH_MTD 188 #define CONFIG_MTD_DEVICE 189 #define CONFIG_MTD_PARTITIONS 190 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 191 #endif 192 /* QSPI reference clock */ 193 #ifndef __ASSEMBLY__ 194 unsigned int cm_get_qspi_controller_clk_hz(void); 195 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 196 #endif 197 #define CONFIG_CQSPI_DECODER 0 198 #define CONFIG_BOUNCE_BUFFER 199 200 /* 201 * Designware SPI support 202 */ 203 204 /* 205 * Serial Driver 206 */ 207 #define CONFIG_SYS_NS16550_SERIAL 208 #define CONFIG_SYS_NS16550_REG_SIZE -4 209 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 210 #define CONFIG_SYS_NS16550_CLK 1000000 211 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5) 212 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 213 #define CONFIG_SYS_NS16550_CLK 100000000 214 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 215 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS 216 #define CONFIG_SYS_NS16550_CLK 50000000 217 #endif 218 #define CONFIG_CONS_INDEX 1 219 220 /* 221 * USB 222 */ 223 224 /* 225 * USB Gadget (DFU, UMS) 226 */ 227 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 228 #define CONFIG_USB_FUNCTION_MASS_STORAGE 229 230 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 231 #define DFU_DEFAULT_POLL_TIMEOUT 300 232 233 /* USB IDs */ 234 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 235 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 236 #endif 237 238 /* 239 * U-Boot environment 240 */ 241 #if !defined(CONFIG_ENV_SIZE) 242 #define CONFIG_ENV_SIZE (8 * 1024) 243 #endif 244 245 /* Environment for SDMMC boot */ 246 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 247 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 248 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 249 #endif 250 251 /* Environment for QSPI boot */ 252 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 253 #define CONFIG_ENV_OFFSET 0x00100000 254 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 255 #endif 256 257 /* 258 * mtd partitioning for serial NOR flash 259 * 260 * device nor0 <ff705000.spi.0>, # parts = 6 261 * #: name size offset mask_flags 262 * 0: u-boot 0x00100000 0x00000000 0 263 * 1: env1 0x00040000 0x00100000 0 264 * 2: env2 0x00040000 0x00140000 0 265 * 3: UBI 0x03e80000 0x00180000 0 266 * 4: boot 0x00e80000 0x00180000 0 267 * 5: rootfs 0x01000000 0x01000000 0 268 * 269 */ 270 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 271 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 272 "1m(u-boot)," \ 273 "256k(env1)," \ 274 "256k(env2)," \ 275 "14848k(boot)," \ 276 "16m(rootfs)," \ 277 "-@1536k(UBI)\0" 278 #endif 279 280 /* 281 * SPL 282 * 283 * SRAM Memory layout: 284 * 285 * 0xFFFF_0000 ...... Start of SRAM 286 * 0xFFFF_xxxx ...... Top of stack (grows down) 287 * 0xFFFF_yyyy ...... Malloc area 288 * 0xFFFF_zzzz ...... Global Data 289 * 0xFFFF_FF00 ...... End of SRAM 290 */ 291 #define CONFIG_SPL_FRAMEWORK 292 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 293 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 294 295 /* SPL SDMMC boot support */ 296 #ifdef CONFIG_SPL_MMC_SUPPORT 297 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 298 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 299 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 300 #endif 301 #else 302 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 303 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 304 #endif 305 #endif 306 307 /* SPL QSPI boot support */ 308 #ifdef CONFIG_SPL_SPI_SUPPORT 309 #define CONFIG_SPL_SPI_LOAD 310 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 311 #endif 312 313 /* SPL NAND boot support */ 314 #ifdef CONFIG_SPL_NAND_SUPPORT 315 #define CONFIG_SYS_NAND_USE_FLASH_BBT 316 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 317 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 318 #endif 319 320 /* 321 * Stack setup 322 */ 323 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 324 325 /* Extra Environment */ 326 #ifndef CONFIG_SPL_BUILD 327 #include <config_distro_defaults.h> 328 329 #ifdef CONFIG_CMD_PXE 330 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 331 #else 332 #define BOOT_TARGET_DEVICES_PXE(func) 333 #endif 334 335 #ifdef CONFIG_CMD_MMC 336 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 337 #else 338 #define BOOT_TARGET_DEVICES_MMC(func) 339 #endif 340 341 #define BOOT_TARGET_DEVICES(func) \ 342 BOOT_TARGET_DEVICES_MMC(func) \ 343 BOOT_TARGET_DEVICES_PXE(func) \ 344 func(DHCP, dhcp, na) 345 346 #include <config_distro_bootcmd.h> 347 348 #ifndef CONFIG_EXTRA_ENV_SETTINGS 349 #define CONFIG_EXTRA_ENV_SETTINGS \ 350 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 351 "bootm_size=0xa000000\0" \ 352 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 353 "fdt_addr_r=0x02000000\0" \ 354 "scriptaddr=0x02100000\0" \ 355 "pxefile_addr_r=0x02200000\0" \ 356 "ramdisk_addr_r=0x02300000\0" \ 357 BOOTENV 358 359 #endif 360 #endif 361 362 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 363