1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 10 /* Virtual target or real hardware */ 11 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 12 13 #define CONFIG_SYS_THUMB_BUILD 14 15 /* 16 * High level configuration 17 */ 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO_LATE 20 #define CONFIG_ARCH_MISC_INIT 21 #define CONFIG_ARCH_EARLY_INIT_R 22 #define CONFIG_SYS_NO_FLASH 23 #define CONFIG_CLOCKS 24 25 #define CONFIG_CRC32_VERIFY 26 27 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* add target to build it automatically upon "make" */ 32 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 33 34 /* 35 * Memory configurations 36 */ 37 #define CONFIG_NR_DRAM_BANKS 1 38 #define PHYS_SDRAM_1 0x0 39 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 40 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 41 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 42 43 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 44 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 45 #define CONFIG_SYS_INIT_SP_OFFSET \ 46 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 47 #define CONFIG_SYS_INIT_SP_ADDR \ 48 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 49 50 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 51 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 52 #define CONFIG_SYS_TEXT_BASE 0x08000040 53 #else 54 #define CONFIG_SYS_TEXT_BASE 0x01000040 55 #endif 56 57 /* 58 * U-Boot general configurations 59 */ 60 #define CONFIG_SYS_LONGHELP 61 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 62 #define CONFIG_SYS_PBSIZE \ 63 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 64 /* Print buffer size */ 65 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 66 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 67 /* Boot argument buffer size */ 68 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 69 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 70 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 71 72 #ifndef CONFIG_SYS_HOSTNAME 73 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 74 #endif 75 76 /* 77 * Cache 78 */ 79 #define CONFIG_SYS_CACHELINE_SIZE 32 80 #define CONFIG_SYS_L2_PL310 81 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 82 83 /* 84 * SDRAM controller 85 */ 86 #define CONFIG_ALTERA_SDRAM 87 88 /* 89 * EPCS/EPCQx1 Serial Flash Controller 90 */ 91 #ifdef CONFIG_ALTERA_SPI 92 #define CONFIG_CMD_SPI 93 #define CONFIG_CMD_SF 94 #define CONFIG_SF_DEFAULT_SPEED 30000000 95 /* 96 * The base address is configurable in QSys, each board must specify the 97 * base address based on it's particular FPGA configuration. Please note 98 * that the address here is incremented by 0x400 from the Base address 99 * selected in QSys, since the SPI registers are at offset +0x400. 100 * #define CONFIG_SYS_SPI_BASE 0xff240400 101 */ 102 #endif 103 104 /* 105 * Ethernet on SoC (EMAC) 106 */ 107 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 108 #define CONFIG_DW_ALTDESCRIPTOR 109 #define CONFIG_MII 110 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 111 #define CONFIG_PHY_GIGE 112 #endif 113 114 /* 115 * FPGA Driver 116 */ 117 #ifdef CONFIG_CMD_FPGA 118 #define CONFIG_FPGA 119 #define CONFIG_FPGA_ALTERA 120 #define CONFIG_FPGA_SOCFPGA 121 #define CONFIG_FPGA_COUNT 1 122 #endif 123 124 /* 125 * L4 OSC1 Timer 0 126 */ 127 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 128 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 129 #define CONFIG_SYS_TIMER_COUNTS_DOWN 130 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 131 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 132 #define CONFIG_SYS_TIMER_RATE 2400000 133 #else 134 #define CONFIG_SYS_TIMER_RATE 25000000 135 #endif 136 137 /* 138 * L4 Watchdog 139 */ 140 #ifdef CONFIG_HW_WATCHDOG 141 #define CONFIG_DESIGNWARE_WATCHDOG 142 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 143 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 144 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 145 #endif 146 147 /* 148 * MMC Driver 149 */ 150 #ifdef CONFIG_CMD_MMC 151 #define CONFIG_MMC 152 #define CONFIG_BOUNCE_BUFFER 153 #define CONFIG_GENERIC_MMC 154 #define CONFIG_DWMMC 155 #define CONFIG_SOCFPGA_DWMMC 156 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 157 /* FIXME */ 158 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 159 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 160 #endif 161 162 /* 163 * NAND Support 164 */ 165 #ifdef CONFIG_NAND_DENALI 166 #define CONFIG_SYS_MAX_NAND_DEVICE 1 167 #define CONFIG_SYS_NAND_MAX_CHIPS 1 168 #define CONFIG_SYS_NAND_ONFI_DETECTION 169 #define CONFIG_NAND_DENALI_ECC_SIZE 512 170 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 171 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 172 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 173 #endif 174 175 /* 176 * I2C support 177 */ 178 #define CONFIG_SYS_I2C 179 #define CONFIG_SYS_I2C_DW 180 #define CONFIG_SYS_I2C_BUS_MAX 4 181 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 182 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 183 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 184 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 185 /* Using standard mode which the speed up to 100Kb/s */ 186 #define CONFIG_SYS_I2C_SPEED 100000 187 #define CONFIG_SYS_I2C_SPEED1 100000 188 #define CONFIG_SYS_I2C_SPEED2 100000 189 #define CONFIG_SYS_I2C_SPEED3 100000 190 /* Address of device when used as slave */ 191 #define CONFIG_SYS_I2C_SLAVE 0x02 192 #define CONFIG_SYS_I2C_SLAVE1 0x02 193 #define CONFIG_SYS_I2C_SLAVE2 0x02 194 #define CONFIG_SYS_I2C_SLAVE3 0x02 195 #ifndef __ASSEMBLY__ 196 /* Clock supplied to I2C controller in unit of MHz */ 197 unsigned int cm_get_l4_sp_clk_hz(void); 198 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 199 #endif 200 #define CONFIG_CMD_I2C 201 202 /* 203 * QSPI support 204 */ 205 /* Enable multiple SPI NOR flash manufacturers */ 206 #ifndef CONFIG_SPL_BUILD 207 #define CONFIG_SPI_FLASH_MTD 208 #define CONFIG_CMD_MTDPARTS 209 #define CONFIG_MTD_DEVICE 210 #define CONFIG_MTD_PARTITIONS 211 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 212 #endif 213 /* QSPI reference clock */ 214 #ifndef __ASSEMBLY__ 215 unsigned int cm_get_qspi_controller_clk_hz(void); 216 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 217 #endif 218 #define CONFIG_CQSPI_DECODER 0 219 #define CONFIG_CMD_SF 220 221 /* 222 * Designware SPI support 223 */ 224 #define CONFIG_CMD_SPI 225 226 /* 227 * Serial Driver 228 */ 229 #define CONFIG_SYS_NS16550_SERIAL 230 #define CONFIG_SYS_NS16550_REG_SIZE -4 231 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 232 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 233 #define CONFIG_SYS_NS16550_CLK 1000000 234 #else 235 #define CONFIG_SYS_NS16550_CLK 100000000 236 #endif 237 #define CONFIG_CONS_INDEX 1 238 #define CONFIG_BAUDRATE 115200 239 240 /* 241 * USB 242 */ 243 #ifdef CONFIG_CMD_USB 244 #define CONFIG_USB_DWC2 245 #define CONFIG_USB_STORAGE 246 #endif 247 248 /* 249 * USB Gadget (DFU, UMS) 250 */ 251 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 252 #define CONFIG_USB_FUNCTION_MASS_STORAGE 253 254 #define CONFIG_USB_FUNCTION_DFU 255 #ifdef CONFIG_DM_MMC 256 #define CONFIG_DFU_MMC 257 #endif 258 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) 259 #define DFU_DEFAULT_POLL_TIMEOUT 300 260 261 /* USB IDs */ 262 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 263 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 264 #endif 265 266 /* 267 * U-Boot environment 268 */ 269 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 270 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 271 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 272 #if !defined(CONFIG_ENV_SIZE) 273 #define CONFIG_ENV_SIZE 4096 274 #endif 275 276 /* Environment for SDMMC boot */ 277 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 278 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 279 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ 280 #endif 281 282 /* Environment for QSPI boot */ 283 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 284 #define CONFIG_ENV_OFFSET 0x00100000 285 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 286 #endif 287 288 /* 289 * mtd partitioning for serial NOR flash 290 * 291 * device nor0 <ff705000.spi.0>, # parts = 6 292 * #: name size offset mask_flags 293 * 0: u-boot 0x00100000 0x00000000 0 294 * 1: env1 0x00040000 0x00100000 0 295 * 2: env2 0x00040000 0x00140000 0 296 * 3: UBI 0x03e80000 0x00180000 0 297 * 4: boot 0x00e80000 0x00180000 0 298 * 5: rootfs 0x01000000 0x01000000 0 299 * 300 */ 301 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 302 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 303 "1m(u-boot)," \ 304 "256k(env1)," \ 305 "256k(env2)," \ 306 "14848k(boot)," \ 307 "16m(rootfs)," \ 308 "-@1536k(UBI)\0" 309 #endif 310 311 /* UBI and UBIFS support */ 312 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) 313 #define CONFIG_CMD_UBI 314 #define CONFIG_CMD_UBIFS 315 #define CONFIG_RBTREE 316 #define CONFIG_LZO 317 #endif 318 319 /* 320 * SPL 321 * 322 * SRAM Memory layout: 323 * 324 * 0xFFFF_0000 ...... Start of SRAM 325 * 0xFFFF_xxxx ...... Top of stack (grows down) 326 * 0xFFFF_yyyy ...... Malloc area 327 * 0xFFFF_zzzz ...... Global Data 328 * 0xFFFF_FF00 ...... End of SRAM 329 */ 330 #define CONFIG_SPL_FRAMEWORK 331 #define CONFIG_SPL_RAM_DEVICE 332 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 333 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 334 #ifdef CONFIG_SPL_BUILD 335 #define CONFIG_SYS_MALLOC_SIMPLE 336 #endif 337 338 #define CONFIG_SPL_LIBCOMMON_SUPPORT 339 #define CONFIG_SPL_LIBGENERIC_SUPPORT 340 #define CONFIG_SPL_WATCHDOG_SUPPORT 341 #define CONFIG_SPL_SERIAL_SUPPORT 342 #ifdef CONFIG_DM_MMC 343 #define CONFIG_SPL_MMC_SUPPORT 344 #endif 345 #ifdef CONFIG_DM_SPI 346 #define CONFIG_SPL_SPI_SUPPORT 347 #endif 348 #ifdef CONFIG_SPL_NAND_DENALI 349 #define CONFIG_SPL_NAND_SUPPORT 350 #endif 351 352 /* SPL SDMMC boot support */ 353 #ifdef CONFIG_SPL_MMC_SUPPORT 354 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 355 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 356 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 357 #define CONFIG_SPL_LIBDISK_SUPPORT 358 #else 359 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 360 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ 361 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ 362 #endif 363 #endif 364 365 /* SPL QSPI boot support */ 366 #ifdef CONFIG_SPL_SPI_SUPPORT 367 #define CONFIG_SPL_SPI_FLASH_SUPPORT 368 #define CONFIG_SPL_SPI_LOAD 369 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 370 #endif 371 372 /* SPL NAND boot support */ 373 #ifdef CONFIG_SPL_NAND_SUPPORT 374 #define CONFIG_SYS_NAND_USE_FLASH_BBT 375 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 376 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 377 #endif 378 379 /* 380 * Stack setup 381 */ 382 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 383 384 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 385