1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 10 /* Virtual target or real hardware */ 11 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 12 13 #define CONFIG_SYS_THUMB_BUILD 14 15 /* 16 * High level configuration 17 */ 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO_LATE 20 #define CONFIG_ARCH_MISC_INIT 21 #define CONFIG_ARCH_EARLY_INIT_R 22 #define CONFIG_SYS_NO_FLASH 23 #define CONFIG_CLOCKS 24 25 #define CONFIG_CRC32_VERIFY 26 27 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* add target to build it automatically upon "make" */ 32 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 33 34 /* 35 * Memory configurations 36 */ 37 #define CONFIG_NR_DRAM_BANKS 1 38 #define PHYS_SDRAM_1 0x0 39 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 40 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 41 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 42 43 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 44 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 45 #define CONFIG_SYS_INIT_SP_OFFSET \ 46 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 47 #define CONFIG_SYS_INIT_SP_ADDR \ 48 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 49 50 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 51 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 52 #define CONFIG_SYS_TEXT_BASE 0x08000040 53 #else 54 #define CONFIG_SYS_TEXT_BASE 0x01000040 55 #endif 56 57 /* 58 * U-Boot general configurations 59 */ 60 #define CONFIG_SYS_LONGHELP 61 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 62 #define CONFIG_SYS_PBSIZE \ 63 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 64 /* Print buffer size */ 65 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 66 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 67 /* Boot argument buffer size */ 68 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 69 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 70 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 71 #define CONFIG_SYS_HUSH_PARSER 72 73 #ifndef CONFIG_SYS_HOSTNAME 74 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 75 #endif 76 77 /* 78 * Cache 79 */ 80 #define CONFIG_SYS_CACHELINE_SIZE 32 81 #define CONFIG_SYS_L2_PL310 82 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 83 84 /* 85 * SDRAM controller 86 */ 87 #define CONFIG_ALTERA_SDRAM 88 89 /* 90 * EPCS/EPCQx1 Serial Flash Controller 91 */ 92 #ifdef CONFIG_ALTERA_SPI 93 #define CONFIG_CMD_SPI 94 #define CONFIG_CMD_SF 95 #define CONFIG_SF_DEFAULT_SPEED 30000000 96 /* 97 * The base address is configurable in QSys, each board must specify the 98 * base address based on it's particular FPGA configuration. Please note 99 * that the address here is incremented by 0x400 from the Base address 100 * selected in QSys, since the SPI registers are at offset +0x400. 101 * #define CONFIG_SYS_SPI_BASE 0xff240400 102 */ 103 #endif 104 105 /* 106 * Ethernet on SoC (EMAC) 107 */ 108 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 109 #define CONFIG_DW_ALTDESCRIPTOR 110 #define CONFIG_MII 111 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 112 #define CONFIG_PHY_GIGE 113 #endif 114 115 /* 116 * FPGA Driver 117 */ 118 #ifdef CONFIG_CMD_FPGA 119 #define CONFIG_FPGA 120 #define CONFIG_FPGA_ALTERA 121 #define CONFIG_FPGA_SOCFPGA 122 #define CONFIG_FPGA_COUNT 1 123 #endif 124 125 /* 126 * L4 OSC1 Timer 0 127 */ 128 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 129 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 130 #define CONFIG_SYS_TIMER_COUNTS_DOWN 131 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 132 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 133 #define CONFIG_SYS_TIMER_RATE 2400000 134 #else 135 #define CONFIG_SYS_TIMER_RATE 25000000 136 #endif 137 138 /* 139 * L4 Watchdog 140 */ 141 #ifdef CONFIG_HW_WATCHDOG 142 #define CONFIG_DESIGNWARE_WATCHDOG 143 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 144 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 145 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 146 #endif 147 148 /* 149 * MMC Driver 150 */ 151 #ifdef CONFIG_CMD_MMC 152 #define CONFIG_MMC 153 #define CONFIG_BOUNCE_BUFFER 154 #define CONFIG_GENERIC_MMC 155 #define CONFIG_DWMMC 156 #define CONFIG_SOCFPGA_DWMMC 157 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 158 /* FIXME */ 159 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 160 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 161 #endif 162 163 /* 164 * NAND Support 165 */ 166 #ifdef CONFIG_NAND_DENALI 167 #define CONFIG_SYS_MAX_NAND_DEVICE 1 168 #define CONFIG_SYS_NAND_MAX_CHIPS 1 169 #define CONFIG_SYS_NAND_ONFI_DETECTION 170 #define CONFIG_NAND_DENALI_ECC_SIZE 512 171 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 172 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 173 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 174 #endif 175 176 /* 177 * I2C support 178 */ 179 #define CONFIG_SYS_I2C 180 #define CONFIG_SYS_I2C_DW 181 #define CONFIG_SYS_I2C_BUS_MAX 4 182 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 183 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 184 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 185 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 186 /* Using standard mode which the speed up to 100Kb/s */ 187 #define CONFIG_SYS_I2C_SPEED 100000 188 #define CONFIG_SYS_I2C_SPEED1 100000 189 #define CONFIG_SYS_I2C_SPEED2 100000 190 #define CONFIG_SYS_I2C_SPEED3 100000 191 /* Address of device when used as slave */ 192 #define CONFIG_SYS_I2C_SLAVE 0x02 193 #define CONFIG_SYS_I2C_SLAVE1 0x02 194 #define CONFIG_SYS_I2C_SLAVE2 0x02 195 #define CONFIG_SYS_I2C_SLAVE3 0x02 196 #ifndef __ASSEMBLY__ 197 /* Clock supplied to I2C controller in unit of MHz */ 198 unsigned int cm_get_l4_sp_clk_hz(void); 199 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 200 #endif 201 #define CONFIG_CMD_I2C 202 203 /* 204 * QSPI support 205 */ 206 /* Enable multiple SPI NOR flash manufacturers */ 207 #ifndef CONFIG_SPL_BUILD 208 #define CONFIG_SPI_FLASH_MTD 209 #define CONFIG_CMD_MTDPARTS 210 #define CONFIG_MTD_DEVICE 211 #define CONFIG_MTD_PARTITIONS 212 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 213 #endif 214 /* QSPI reference clock */ 215 #ifndef __ASSEMBLY__ 216 unsigned int cm_get_qspi_controller_clk_hz(void); 217 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 218 #endif 219 #define CONFIG_CQSPI_DECODER 0 220 #define CONFIG_CMD_SF 221 222 /* 223 * Designware SPI support 224 */ 225 #define CONFIG_CMD_SPI 226 227 /* 228 * Serial Driver 229 */ 230 #define CONFIG_SYS_NS16550_SERIAL 231 #define CONFIG_SYS_NS16550_REG_SIZE -4 232 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 233 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 234 #define CONFIG_SYS_NS16550_CLK 1000000 235 #else 236 #define CONFIG_SYS_NS16550_CLK 100000000 237 #endif 238 #define CONFIG_CONS_INDEX 1 239 #define CONFIG_BAUDRATE 115200 240 241 /* 242 * USB 243 */ 244 #ifdef CONFIG_CMD_USB 245 #define CONFIG_USB_DWC2 246 #define CONFIG_USB_STORAGE 247 #endif 248 249 /* 250 * USB Gadget (DFU, UMS) 251 */ 252 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 253 #define CONFIG_USB_GADGET_DWC2_OTG 254 #define CONFIG_USB_GADGET_DUALSPEED 255 256 /* USB Composite download gadget - g_dnl */ 257 #define CONFIG_USB_GADGET_DOWNLOAD 258 #define CONFIG_USB_FUNCTION_MASS_STORAGE 259 260 #define CONFIG_USB_FUNCTION_DFU 261 #ifdef CONFIG_DM_MMC 262 #define CONFIG_DFU_MMC 263 #endif 264 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) 265 #define DFU_DEFAULT_POLL_TIMEOUT 300 266 267 /* USB IDs */ 268 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ 269 #define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ 270 #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM 271 #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM 272 #ifndef CONFIG_G_DNL_MANUFACTURER 273 #define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR 274 #endif 275 #endif 276 277 /* 278 * U-Boot environment 279 */ 280 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 281 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 282 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 283 #if !defined(CONFIG_ENV_SIZE) 284 #define CONFIG_ENV_SIZE 4096 285 #endif 286 287 /* Environment for SDMMC boot */ 288 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 289 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 290 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ 291 #endif 292 293 /* Environment for QSPI boot */ 294 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 295 #define CONFIG_ENV_OFFSET 0x00100000 296 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 297 #endif 298 299 /* 300 * mtd partitioning for serial NOR flash 301 * 302 * device nor0 <ff705000.spi.0>, # parts = 6 303 * #: name size offset mask_flags 304 * 0: u-boot 0x00100000 0x00000000 0 305 * 1: env1 0x00040000 0x00100000 0 306 * 2: env2 0x00040000 0x00140000 0 307 * 3: UBI 0x03e80000 0x00180000 0 308 * 4: boot 0x00e80000 0x00180000 0 309 * 5: rootfs 0x01000000 0x01000000 0 310 * 311 */ 312 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 313 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 314 "1m(u-boot)," \ 315 "256k(env1)," \ 316 "256k(env2)," \ 317 "14848k(boot)," \ 318 "16m(rootfs)," \ 319 "-@1536k(UBI)\0" 320 #endif 321 322 /* UBI and UBIFS support */ 323 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) 324 #define CONFIG_CMD_UBI 325 #define CONFIG_CMD_UBIFS 326 #define CONFIG_RBTREE 327 #define CONFIG_LZO 328 #endif 329 330 /* 331 * SPL 332 * 333 * SRAM Memory layout: 334 * 335 * 0xFFFF_0000 ...... Start of SRAM 336 * 0xFFFF_xxxx ...... Top of stack (grows down) 337 * 0xFFFF_yyyy ...... Malloc area 338 * 0xFFFF_zzzz ...... Global Data 339 * 0xFFFF_FF00 ...... End of SRAM 340 */ 341 #define CONFIG_SPL_FRAMEWORK 342 #define CONFIG_SPL_RAM_DEVICE 343 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 344 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 345 #ifdef CONFIG_SPL_BUILD 346 #define CONFIG_SYS_MALLOC_SIMPLE 347 #endif 348 349 #define CONFIG_SPL_LIBCOMMON_SUPPORT 350 #define CONFIG_SPL_LIBGENERIC_SUPPORT 351 #define CONFIG_SPL_WATCHDOG_SUPPORT 352 #define CONFIG_SPL_SERIAL_SUPPORT 353 #ifdef CONFIG_DM_MMC 354 #define CONFIG_SPL_MMC_SUPPORT 355 #endif 356 #ifdef CONFIG_DM_SPI 357 #define CONFIG_SPL_SPI_SUPPORT 358 #endif 359 #ifdef CONFIG_SPL_NAND_DENALI 360 #define CONFIG_SPL_NAND_SUPPORT 361 #endif 362 363 /* SPL SDMMC boot support */ 364 #ifdef CONFIG_SPL_MMC_SUPPORT 365 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 366 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 367 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 368 #define CONFIG_SPL_LIBDISK_SUPPORT 369 #else 370 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 371 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ 372 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ 373 #endif 374 #endif 375 376 /* SPL QSPI boot support */ 377 #ifdef CONFIG_SPL_SPI_SUPPORT 378 #define CONFIG_SPL_SPI_FLASH_SUPPORT 379 #define CONFIG_SPL_SPI_LOAD 380 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 381 #endif 382 383 /* SPL NAND boot support */ 384 #ifdef CONFIG_SPL_NAND_SUPPORT 385 #define CONFIG_SYS_NAND_USE_FLASH_BBT 386 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 387 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 388 #endif 389 390 /* 391 * Stack setup 392 */ 393 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 394 395 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 396