13b7f0e10SVladimir Barinov /* 23b7f0e10SVladimir Barinov * include/configs/silk.h 33b7f0e10SVladimir Barinov * This file is silk board configuration. 43b7f0e10SVladimir Barinov * 53b7f0e10SVladimir Barinov * Copyright (C) 2015 Renesas Electronics Corporation 63b7f0e10SVladimir Barinov * Copyright (C) 2015 Cogent Embedded, Inc. 73b7f0e10SVladimir Barinov * 83b7f0e10SVladimir Barinov * SPDX-License-Identifier: GPL-2.0 93b7f0e10SVladimir Barinov */ 103b7f0e10SVladimir Barinov 113b7f0e10SVladimir Barinov #ifndef __SILK_H 123b7f0e10SVladimir Barinov #define __SILK_H 133b7f0e10SVladimir Barinov 143b7f0e10SVladimir Barinov #undef DEBUG 153b7f0e10SVladimir Barinov #define CONFIG_R8A7794 16*1cc95f6eSNobuhiro Iwamatsu #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Silk" 173b7f0e10SVladimir Barinov 183b7f0e10SVladimir Barinov #include "rcar-gen2-common.h" 193b7f0e10SVladimir Barinov 20*1cc95f6eSNobuhiro Iwamatsu #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 213b7f0e10SVladimir Barinov #define CONFIG_SYS_TEXT_BASE 0x70000000 223b7f0e10SVladimir Barinov #else 233b7f0e10SVladimir Barinov #define CONFIG_SYS_TEXT_BASE 0xE6304000 243b7f0e10SVladimir Barinov #endif 253b7f0e10SVladimir Barinov 26*1cc95f6eSNobuhiro Iwamatsu #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 273b7f0e10SVladimir Barinov #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC 283b7f0e10SVladimir Barinov #else 293b7f0e10SVladimir Barinov #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC 303b7f0e10SVladimir Barinov #endif 313b7f0e10SVladimir Barinov #define STACK_AREA_SIZE 0xC000 323b7f0e10SVladimir Barinov #define LOW_LEVEL_MERAM_STACK \ 333b7f0e10SVladimir Barinov (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 343b7f0e10SVladimir Barinov 353b7f0e10SVladimir Barinov /* MEMORY */ 363b7f0e10SVladimir Barinov #define RCAR_GEN2_SDRAM_BASE 0x40000000 373b7f0e10SVladimir Barinov #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) 383b7f0e10SVladimir Barinov #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 393b7f0e10SVladimir Barinov 403b7f0e10SVladimir Barinov /* SCIF */ 413b7f0e10SVladimir Barinov #define CONFIG_SCIF_CONSOLE 423b7f0e10SVladimir Barinov 433b7f0e10SVladimir Barinov /* FLASH */ 443b7f0e10SVladimir Barinov #define CONFIG_SPI 453b7f0e10SVladimir Barinov #define CONFIG_SH_QSPI 463b7f0e10SVladimir Barinov #define CONFIG_SPI_FLASH_QUAD 473b7f0e10SVladimir Barinov #define CONFIG_SYS_NO_FLASH 483b7f0e10SVladimir Barinov 493b7f0e10SVladimir Barinov /* SH Ether */ 503b7f0e10SVladimir Barinov #define CONFIG_SH_ETHER 513b7f0e10SVladimir Barinov #define CONFIG_SH_ETHER_USE_PORT 0 523b7f0e10SVladimir Barinov #define CONFIG_SH_ETHER_PHY_ADDR 0x1 533b7f0e10SVladimir Barinov #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 543b7f0e10SVladimir Barinov #define CONFIG_SH_ETHER_CACHE_WRITEBACK 553b7f0e10SVladimir Barinov #define CONFIG_SH_ETHER_CACHE_INVALIDATE 563b7f0e10SVladimir Barinov #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 573b7f0e10SVladimir Barinov #define CONFIG_PHYLIB 583b7f0e10SVladimir Barinov #define CONFIG_PHY_MICREL 593b7f0e10SVladimir Barinov #define CONFIG_BITBANGMII 603b7f0e10SVladimir Barinov #define CONFIG_BITBANGMII_MULTI 613b7f0e10SVladimir Barinov 623b7f0e10SVladimir Barinov /* Board Clock */ 633b7f0e10SVladimir Barinov #define RMOBILE_XTAL_CLK 20000000u 643b7f0e10SVladimir Barinov #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 653b7f0e10SVladimir Barinov #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 663b7f0e10SVladimir Barinov #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 673b7f0e10SVladimir Barinov #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) 683b7f0e10SVladimir Barinov 693b7f0e10SVladimir Barinov #define CONFIG_SYS_TMU_CLK_DIV 4 703b7f0e10SVladimir Barinov 713b7f0e10SVladimir Barinov /* i2c */ 723b7f0e10SVladimir Barinov #define CONFIG_SYS_I2C 733b7f0e10SVladimir Barinov #define CONFIG_SYS_I2C_SH 743b7f0e10SVladimir Barinov #define CONFIG_SYS_I2C_SLAVE 0x7F 753b7f0e10SVladimir Barinov #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 763b7f0e10SVladimir Barinov #define CONFIG_SYS_I2C_SH_SPEED0 400000 773b7f0e10SVladimir Barinov #define CONFIG_SYS_I2C_SH_SPEED1 400000 783b7f0e10SVladimir Barinov #define CONFIG_SYS_I2C_SH_SPEED2 400000 793b7f0e10SVladimir Barinov #define CONFIG_SH_I2C_DATA_HIGH 4 803b7f0e10SVladimir Barinov #define CONFIG_SH_I2C_DATA_LOW 5 813b7f0e10SVladimir Barinov #define CONFIG_SH_I2C_CLOCK 10000000 823b7f0e10SVladimir Barinov 833b7f0e10SVladimir Barinov #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 843b7f0e10SVladimir Barinov 853b7f0e10SVladimir Barinov /* USB */ 863b7f0e10SVladimir Barinov #define CONFIG_USB_STORAGE 873b7f0e10SVladimir Barinov #define CONFIG_USB_EHCI 883b7f0e10SVladimir Barinov #define CONFIG_USB_EHCI_RMOBILE 893b7f0e10SVladimir Barinov #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 903b7f0e10SVladimir Barinov 913b7f0e10SVladimir Barinov /* MMCIF */ 923b7f0e10SVladimir Barinov #define CONFIG_MMC 933b7f0e10SVladimir Barinov #define CONFIG_GENERIC_MMC 943b7f0e10SVladimir Barinov #define CONFIG_SH_MMCIF 953b7f0e10SVladimir Barinov #define CONFIG_SH_MMCIF_ADDR 0xee200000 963b7f0e10SVladimir Barinov #define CONFIG_SH_MMCIF_CLK 48000000 973b7f0e10SVladimir Barinov 98275ec28eSVladimir Barinov /* SDHI */ 99275ec28eSVladimir Barinov #define CONFIG_SH_SDHI_FREQ 97500000 100275ec28eSVladimir Barinov 1013b7f0e10SVladimir Barinov /* Module stop status bits */ 1023b7f0e10SVladimir Barinov /* INTC-RT */ 1033b7f0e10SVladimir Barinov #define CONFIG_SMSTP0_ENA 0x00400000 1043b7f0e10SVladimir Barinov /* MSIF */ 1053b7f0e10SVladimir Barinov #define CONFIG_SMSTP2_ENA 0x00002000 1063b7f0e10SVladimir Barinov /* INTC-SYS, IRQC */ 1073b7f0e10SVladimir Barinov #define CONFIG_SMSTP4_ENA 0x00000180 1083b7f0e10SVladimir Barinov /* SCIF2 */ 1093b7f0e10SVladimir Barinov #define CONFIG_SMSTP7_ENA 0x00080000 1103b7f0e10SVladimir Barinov 1113b7f0e10SVladimir Barinov #endif /* __SILK_H */ 112