1 /* 2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7785LCR_H 10 #define __SH7785LCR_H 11 12 #define CONFIG_CPU_SH7785 1 13 #define CONFIG_SH7785LCR 1 14 15 #define CONFIG_CMD_SH_ZIMAGEBOOT 16 17 #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" 18 19 #define CONFIG_EXTRA_ENV_SETTINGS \ 20 "bootdevice=0:1\0" \ 21 "usbload=usb reset;usbboot;usb stop;bootm\0" 22 23 #define CONFIG_DISPLAY_BOARDINFO 24 #undef CONFIG_SHOW_BOOT_PROGRESS 25 26 /* MEMORY */ 27 #if defined(CONFIG_SH_32BIT) 28 #define CONFIG_SYS_TEXT_BASE 0x8FF80000 29 /* 0x40000000 - 0x47FFFFFF does not use */ 30 #define CONFIG_SH_SDRAM_OFFSET (0x8000000) 31 #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 32 #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 33 #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) 34 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 35 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 36 #define SH7785LCR_USB_BASE (0xa6000000) 37 #else 38 #define CONFIG_SYS_TEXT_BASE 0x0FF80000 39 #define SH7785LCR_SDRAM_BASE (0x08000000) 40 #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) 41 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 42 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 43 #define SH7785LCR_USB_BASE (0xb4000000) 44 #endif 45 46 #define CONFIG_SYS_LONGHELP 47 #define CONFIG_SYS_CBSIZE 256 48 #define CONFIG_SYS_PBSIZE 256 49 #define CONFIG_SYS_MAXARGS 16 50 #define CONFIG_SYS_BARGSIZE 512 51 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 52 53 /* SCIF */ 54 #define CONFIG_CONS_SCIF1 1 55 #define CONFIG_SCIF_EXT_CLOCK 1 56 57 #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) 58 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 59 (SH7785LCR_SDRAM_SIZE) - \ 60 4 * 1024 * 1024) 61 #undef CONFIG_SYS_ALT_MEMTEST 62 #undef CONFIG_SYS_MEMTEST_SCRATCH 63 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 64 65 #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) 66 #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) 67 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 68 69 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) 70 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 71 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 72 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 73 74 /* FLASH */ 75 #define CONFIG_FLASH_CFI_DRIVER 76 #define CONFIG_SYS_FLASH_CFI 77 #undef CONFIG_SYS_FLASH_QUIET_TEST 78 #define CONFIG_SYS_FLASH_EMPTY_INFO 79 #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) 80 #define CONFIG_SYS_MAX_FLASH_SECT 512 81 82 #define CONFIG_SYS_MAX_FLASH_BANKS 1 83 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ 84 (0 * SH7785LCR_FLASH_BANK_SIZE) } 85 86 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 87 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 88 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 89 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 90 91 #undef CONFIG_SYS_FLASH_PROTECTION 92 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 93 94 /* R8A66597 */ 95 #define CONFIG_USB_R8A66597_HCD 96 #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE 97 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 98 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 99 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 100 101 /* PCI Controller */ 102 #define CONFIG_SH4_PCI 103 #define CONFIG_SH7780_PCI 104 #if defined(CONFIG_SH_32BIT) 105 #define CONFIG_SH7780_PCI_LSR 0x1ff00001 106 #define CONFIG_SH7780_PCI_LAR 0x5f000000 107 #define CONFIG_SH7780_PCI_BAR 0x5f000000 108 #else 109 #define CONFIG_SH7780_PCI_LSR 0x07f00001 110 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 111 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 112 #endif 113 #define CONFIG_PCI_SCAN_SHOW 1 114 115 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 116 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 117 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 118 119 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 120 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 121 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 122 123 #if defined(CONFIG_SH_32BIT) 124 #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE 125 #else 126 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 127 #endif 128 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 129 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 130 131 /* ENV setting */ 132 #define CONFIG_ENV_OVERWRITE 1 133 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 134 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 135 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 136 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 137 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 138 139 /* Board Clock */ 140 /* The SCIF used external clock. system clock only used timer. */ 141 #define CONFIG_SYS_CLK_FREQ 50000000 142 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 143 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 144 #define CONFIG_SYS_TMU_CLK_DIV 4 145 146 #endif /* __SH7785LCR_H */ 147