1 /* 2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board 3 * 4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7785LCR_H 10 #define __SH7785LCR_H 11 12 #undef DEBUG 13 #define CONFIG_CPU_SH7785 1 14 #define CONFIG_SH7785LCR 1 15 16 #define CONFIG_CMD_PCI 17 #define CONFIG_CMD_SDRAM 18 #define CONFIG_CMD_SH_ZIMAGEBOOT 19 20 #define CONFIG_USB_STORAGE 21 #define CONFIG_CMD_EXT2 22 #define CONFIG_CMD_FAT 23 #define CONFIG_DOS_PARTITION 24 #define CONFIG_MAC_PARTITION 25 26 #define CONFIG_BAUDRATE 115200 27 #define CONFIG_BOOTDELAY 3 28 #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" 29 30 #define CONFIG_EXTRA_ENV_SETTINGS \ 31 "bootdevice=0:1\0" \ 32 "usbload=usb reset;usbboot;usb stop;bootm\0" 33 34 #define CONFIG_VERSION_VARIABLE 35 #undef CONFIG_SHOW_BOOT_PROGRESS 36 37 /* MEMORY */ 38 #if defined(CONFIG_SH_32BIT) 39 #define CONFIG_SYS_TEXT_BASE 0x8FF80000 40 /* 0x40000000 - 0x47FFFFFF does not use */ 41 #define CONFIG_SH_SDRAM_OFFSET (0x8000000) 42 #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) 43 #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) 44 #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) 45 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 46 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 47 #define SH7785LCR_USB_BASE (0xa6000000) 48 #else 49 #define CONFIG_SYS_TEXT_BASE 0x0FF80000 50 #define SH7785LCR_SDRAM_BASE (0x08000000) 51 #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) 52 #define SH7785LCR_FLASH_BASE_1 (0xa0000000) 53 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) 54 #define SH7785LCR_USB_BASE (0xb4000000) 55 #endif 56 57 #define CONFIG_SYS_LONGHELP 58 #define CONFIG_SYS_CBSIZE 256 59 #define CONFIG_SYS_PBSIZE 256 60 #define CONFIG_SYS_MAXARGS 16 61 #define CONFIG_SYS_BARGSIZE 512 62 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 63 64 /* SCIF */ 65 #define CONFIG_SCIF_CONSOLE 1 66 #define CONFIG_CONS_SCIF1 1 67 #define CONFIG_SCIF_EXT_CLOCK 1 68 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 69 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 70 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 71 72 73 #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) 74 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 75 (SH7785LCR_SDRAM_SIZE) - \ 76 4 * 1024 * 1024) 77 #undef CONFIG_SYS_ALT_MEMTEST 78 #undef CONFIG_SYS_MEMTEST_SCRATCH 79 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 80 81 #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) 82 #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) 83 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 84 85 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) 86 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 87 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 88 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 89 90 /* FLASH */ 91 #define CONFIG_FLASH_CFI_DRIVER 92 #define CONFIG_SYS_FLASH_CFI 93 #undef CONFIG_SYS_FLASH_QUIET_TEST 94 #define CONFIG_SYS_FLASH_EMPTY_INFO 95 #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) 96 #define CONFIG_SYS_MAX_FLASH_SECT 512 97 98 #define CONFIG_SYS_MAX_FLASH_BANKS 1 99 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ 100 (0 * SH7785LCR_FLASH_BANK_SIZE) } 101 102 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 103 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 104 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 105 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 106 107 #undef CONFIG_SYS_FLASH_PROTECTION 108 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 109 110 /* R8A66597 */ 111 #define CONFIG_USB_R8A66597_HCD 112 #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE 113 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 114 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 115 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 116 117 /* PCI Controller */ 118 #define CONFIG_PCI 119 #define CONFIG_SH4_PCI 120 #define CONFIG_SH7780_PCI 121 #if defined(CONFIG_SH_32BIT) 122 #define CONFIG_SH7780_PCI_LSR 0x1ff00001 123 #define CONFIG_SH7780_PCI_LAR 0x5f000000 124 #define CONFIG_SH7780_PCI_BAR 0x5f000000 125 #else 126 #define CONFIG_SH7780_PCI_LSR 0x07f00001 127 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 128 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 129 #endif 130 #define CONFIG_PCI_PNP 131 #define CONFIG_PCI_SCAN_SHOW 1 132 133 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 134 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 135 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 136 137 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 138 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 139 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 140 141 #if defined(CONFIG_SH_32BIT) 142 #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE 143 #else 144 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 145 #endif 146 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 147 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 148 149 /* ENV setting */ 150 #define CONFIG_ENV_IS_IN_FLASH 151 #define CONFIG_ENV_OVERWRITE 1 152 #define CONFIG_ENV_SECT_SIZE (256 * 1024) 153 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 154 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 155 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 156 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 157 158 /* Board Clock */ 159 /* The SCIF used external clock. system clock only used timer. */ 160 #define CONFIG_SYS_CLK_FREQ 50000000 161 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 162 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 163 #define CONFIG_SYS_TMU_CLK_DIV 4 164 165 #endif /* __SH7785LCR_H */ 166