1 /* 2 * Configuation settings for the sh7757lcr board 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7757LCR_H 10 #define __SH7757LCR_H 11 12 #define CONFIG_CPU_SH7757 1 13 #define CONFIG_SH7757LCR 1 14 #define CONFIG_SH7757LCR_DDR_ECC 1 15 16 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 17 18 #define CONFIG_CMD_SDRAM 19 #define CONFIG_CMD_MD5SUM 20 #define CONFIG_MD5 21 #define CONFIG_DOS_PARTITION 22 23 #define CONFIG_BAUDRATE 115200 24 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" 25 26 #define CONFIG_DISPLAY_BOARDINFO 27 #undef CONFIG_SHOW_BOOT_PROGRESS 28 29 /* MEMORY */ 30 #define SH7757LCR_SDRAM_BASE (0x80000000) 31 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 32 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 33 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 34 35 #define CONFIG_SYS_LONGHELP 36 #define CONFIG_SYS_CBSIZE 256 37 #define CONFIG_SYS_PBSIZE 256 38 #define CONFIG_SYS_MAXARGS 16 39 #define CONFIG_SYS_BARGSIZE 512 40 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 41 42 /* SCIF */ 43 #define CONFIG_SCIF_CONSOLE 1 44 #define CONFIG_CONS_SCIF2 1 45 46 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 47 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 48 224 * 1024 * 1024) 49 #undef CONFIG_SYS_ALT_MEMTEST 50 #undef CONFIG_SYS_MEMTEST_SCRATCH 51 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 52 53 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 54 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 55 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 56 (128 + 16) * 1024 * 1024) 57 58 #define CONFIG_SYS_MONITOR_BASE 0x00000000 59 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 60 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 61 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 62 63 /* FLASH */ 64 #define CONFIG_SYS_NO_FLASH 65 66 /* Ether */ 67 #define CONFIG_SH_ETHER 1 68 #define CONFIG_SH_ETHER_USE_PORT 0 69 #define CONFIG_SH_ETHER_PHY_ADDR 1 70 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 71 #define CONFIG_PHYLIB 72 #define CONFIG_BITBANGMII 73 #define CONFIG_BITBANGMII_MULTI 74 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 75 76 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 77 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 78 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 79 #define SH7757LCR_ETHERNET_MAC_SIZE 17 80 #define SH7757LCR_ETHERNET_NUM_CH 2 81 82 /* Gigabit Ether */ 83 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 84 85 /* SPI */ 86 #define CONFIG_SH_SPI 1 87 #define CONFIG_SH_SPI_BASE 0xfe002000 88 89 /* MMCIF */ 90 #define CONFIG_GENERIC_MMC 1 91 #define CONFIG_SH_MMCIF 1 92 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 93 #define CONFIG_SH_MMCIF_CLK 48000000 94 95 /* SH7757 board */ 96 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 97 #define SH7757LCR_GRA_OFFSET 0x1f000000 98 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 99 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 100 #define SH7757LCR_PCIEBRG_ADDR 0x00090000 101 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 102 103 /* ENV setting */ 104 #define CONFIG_ENV_IS_EMBEDDED 105 #define CONFIG_ENV_IS_IN_SPI_FLASH 106 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 107 #define CONFIG_ENV_ADDR (0x00080000) 108 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 109 #define CONFIG_ENV_OVERWRITE 1 110 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 111 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 112 #define CONFIG_EXTRA_ENV_SETTINGS \ 113 "netboot=bootp; bootm\0" 114 115 /* Board Clock */ 116 #define CONFIG_SYS_CLK_FREQ 48000000 117 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 118 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 119 #define CONFIG_SYS_TMU_CLK_DIV 4 120 #endif /* __SH7757LCR_H */ 121