1 /* 2 * Configuation settings for the sh7757lcr board 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7757LCR_H 10 #define __SH7757LCR_H 11 12 #undef DEBUG 13 #define CONFIG_CPU_SH7757 1 14 #define CONFIG_SH7757LCR 1 15 #define CONFIG_SH7757LCR_DDR_ECC 1 16 17 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 18 #define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds" 19 20 #define CONFIG_CMD_MII 21 #define CONFIG_CMD_SDRAM 22 #define CONFIG_CMD_MD5SUM 23 #define CONFIG_MD5 24 #define CONFIG_CMD_MMC 25 #define CONFIG_CMD_EXT2 26 #define CONFIG_DOS_PARTITION 27 #define CONFIG_MAC_PARTITION 28 29 #define CONFIG_BAUDRATE 115200 30 #define CONFIG_BOOTDELAY 3 31 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" 32 33 #define CONFIG_VERSION_VARIABLE 34 #undef CONFIG_SHOW_BOOT_PROGRESS 35 36 /* MEMORY */ 37 #define SH7757LCR_SDRAM_BASE (0x80000000) 38 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 39 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 40 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 41 42 #define CONFIG_SYS_LONGHELP 43 #define CONFIG_SYS_CBSIZE 256 44 #define CONFIG_SYS_PBSIZE 256 45 #define CONFIG_SYS_MAXARGS 16 46 #define CONFIG_SYS_BARGSIZE 512 47 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 48 49 /* SCIF */ 50 #define CONFIG_SCIF_CONSOLE 1 51 #define CONFIG_CONS_SCIF2 1 52 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 53 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 54 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 55 56 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 57 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 58 224 * 1024 * 1024) 59 #undef CONFIG_SYS_ALT_MEMTEST 60 #undef CONFIG_SYS_MEMTEST_SCRATCH 61 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 62 63 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 64 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 65 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 66 (128 + 16) * 1024 * 1024) 67 68 #define CONFIG_SYS_MONITOR_BASE 0x00000000 69 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 70 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 71 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 72 73 /* FLASH */ 74 #define CONFIG_SYS_NO_FLASH 75 76 /* Ether */ 77 #define CONFIG_SH_ETHER 1 78 #define CONFIG_SH_ETHER_USE_PORT 0 79 #define CONFIG_SH_ETHER_PHY_ADDR 1 80 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 81 #define CONFIG_PHYLIB 82 #define CONFIG_BITBANGMII 83 #define CONFIG_BITBANGMII_MULTI 84 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 85 86 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 87 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 88 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 89 #define SH7757LCR_ETHERNET_MAC_SIZE 17 90 #define SH7757LCR_ETHERNET_NUM_CH 2 91 #define CONFIG_BOARD_LATE_INIT 92 93 /* Gigabit Ether */ 94 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 95 96 /* SPI */ 97 #define CONFIG_SH_SPI 1 98 #define CONFIG_SH_SPI_BASE 0xfe002000 99 100 /* MMCIF */ 101 #define CONFIG_MMC 1 102 #define CONFIG_GENERIC_MMC 1 103 #define CONFIG_SH_MMCIF 1 104 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 105 #define CONFIG_SH_MMCIF_CLK 48000000 106 107 /* SH7757 board */ 108 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 109 #define SH7757LCR_GRA_OFFSET 0x1f000000 110 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 111 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 112 #define SH7757LCR_PCIEBRG_ADDR 0x00090000 113 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 114 115 /* ENV setting */ 116 #define CONFIG_ENV_IS_EMBEDDED 117 #define CONFIG_ENV_IS_IN_SPI_FLASH 118 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 119 #define CONFIG_ENV_ADDR (0x00080000) 120 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 121 #define CONFIG_ENV_OVERWRITE 1 122 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 123 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 124 #define CONFIG_EXTRA_ENV_SETTINGS \ 125 "netboot=bootp; bootm\0" 126 127 /* Board Clock */ 128 #define CONFIG_SYS_CLK_FREQ 48000000 129 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 130 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 131 #define CONFIG_SYS_TMU_CLK_DIV 4 132 #endif /* __SH7757LCR_H */ 133