1 /* 2 * Configuation settings for the sh7757lcr board 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __SH7757LCR_H 10 #define __SH7757LCR_H 11 12 #define CONFIG_CPU_SH7757 1 13 #define CONFIG_SH7757LCR 1 14 #define CONFIG_SH7757LCR_DDR_ECC 1 15 16 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 17 18 #define CONFIG_CMD_SDRAM 19 20 #define CONFIG_BAUDRATE 115200 21 #define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp" 22 23 #define CONFIG_DISPLAY_BOARDINFO 24 #undef CONFIG_SHOW_BOOT_PROGRESS 25 26 /* MEMORY */ 27 #define SH7757LCR_SDRAM_BASE (0x80000000) 28 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 29 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 30 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 31 32 #define CONFIG_SYS_LONGHELP 33 #define CONFIG_SYS_CBSIZE 256 34 #define CONFIG_SYS_PBSIZE 256 35 #define CONFIG_SYS_MAXARGS 16 36 #define CONFIG_SYS_BARGSIZE 512 37 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 38 39 /* SCIF */ 40 #define CONFIG_SCIF_CONSOLE 1 41 #define CONFIG_CONS_SCIF2 1 42 43 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 44 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 45 224 * 1024 * 1024) 46 #undef CONFIG_SYS_ALT_MEMTEST 47 #undef CONFIG_SYS_MEMTEST_SCRATCH 48 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 49 50 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 51 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 52 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 53 (128 + 16) * 1024 * 1024) 54 55 #define CONFIG_SYS_MONITOR_BASE 0x00000000 56 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 57 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 58 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 59 60 /* Ether */ 61 #define CONFIG_SH_ETHER 1 62 #define CONFIG_SH_ETHER_USE_PORT 0 63 #define CONFIG_SH_ETHER_PHY_ADDR 1 64 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 65 #define CONFIG_PHYLIB 66 #define CONFIG_BITBANGMII 67 #define CONFIG_BITBANGMII_MULTI 68 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 69 70 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 71 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 72 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 73 #define SH7757LCR_ETHERNET_MAC_SIZE 17 74 #define SH7757LCR_ETHERNET_NUM_CH 2 75 76 /* Gigabit Ether */ 77 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 78 79 /* SPI */ 80 #define CONFIG_SH_SPI 1 81 #define CONFIG_SH_SPI_BASE 0xfe002000 82 83 /* MMCIF */ 84 #define CONFIG_SH_MMCIF 1 85 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 86 #define CONFIG_SH_MMCIF_CLK 48000000 87 88 /* SH7757 board */ 89 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 90 #define SH7757LCR_GRA_OFFSET 0x1f000000 91 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 92 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 93 #define SH7757LCR_PCIEBRG_ADDR 0x00090000 94 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 95 96 /* ENV setting */ 97 #define CONFIG_ENV_IS_EMBEDDED 98 #define CONFIG_ENV_IS_IN_SPI_FLASH 99 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 100 #define CONFIG_ENV_ADDR (0x00080000) 101 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 102 #define CONFIG_ENV_OVERWRITE 1 103 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 104 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 105 #define CONFIG_EXTRA_ENV_SETTINGS \ 106 "netboot=bootp; bootm\0" 107 108 /* Board Clock */ 109 #define CONFIG_SYS_CLK_FREQ 48000000 110 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 111 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 112 #define CONFIG_SYS_TMU_CLK_DIV 4 113 #endif /* __SH7757LCR_H */ 114