xref: /rk3399_rockchip-uboot/include/configs/sh7753evb.h (revision 99c184906c6e99d402edd816dcb78fcb9ef0f923)
1320cf350SYoshihiro Shimoda /*
2320cf350SYoshihiro Shimoda  * Configuation settings for the sh7753evb board
3320cf350SYoshihiro Shimoda  *
4320cf350SYoshihiro Shimoda  * Copyright (C) 2012 Renesas Solutions Corp.
5320cf350SYoshihiro Shimoda  *
6320cf350SYoshihiro Shimoda  * SPDX-License-Identifier:	GPL-2.0+
7320cf350SYoshihiro Shimoda  */
8320cf350SYoshihiro Shimoda 
9320cf350SYoshihiro Shimoda #ifndef __SH7753EVB_H
10320cf350SYoshihiro Shimoda #define __SH7753EVB_H
11320cf350SYoshihiro Shimoda 
12320cf350SYoshihiro Shimoda #define CONFIG_CPU_SH7753	1
13320cf350SYoshihiro Shimoda #define CONFIG_SH7753EVB	1
14320cf350SYoshihiro Shimoda 
15320cf350SYoshihiro Shimoda #define CONFIG_SYS_TEXT_BASE	0x5ff80000
16320cf350SYoshihiro Shimoda 
17*18a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO
18320cf350SYoshihiro Shimoda #undef	CONFIG_SHOW_BOOT_PROGRESS
19320cf350SYoshihiro Shimoda #define CONFIG_CMDLINE_EDITING
20320cf350SYoshihiro Shimoda #define CONFIG_AUTO_COMPLETE
21320cf350SYoshihiro Shimoda 
22320cf350SYoshihiro Shimoda /* MEMORY */
23320cf350SYoshihiro Shimoda #define SH7753EVB_SDRAM_BASE		(0x40000000)
24320cf350SYoshihiro Shimoda #define SH7753EVB_SDRAM_SIZE		(512 * 1024 * 1024)
25320cf350SYoshihiro Shimoda 
26320cf350SYoshihiro Shimoda #define CONFIG_SYS_LONGHELP
27320cf350SYoshihiro Shimoda #define CONFIG_SYS_PBSIZE		256
28320cf350SYoshihiro Shimoda #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
29320cf350SYoshihiro Shimoda 
30320cf350SYoshihiro Shimoda /* SCIF */
31320cf350SYoshihiro Shimoda #define CONFIG_CONS_SCIF2	1
32320cf350SYoshihiro Shimoda 
33320cf350SYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_START	(SH7753EVB_SDRAM_BASE)
34320cf350SYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
35320cf350SYoshihiro Shimoda 					 480 * 1024 * 1024)
36320cf350SYoshihiro Shimoda #undef	CONFIG_SYS_ALT_MEMTEST
37320cf350SYoshihiro Shimoda #undef	CONFIG_SYS_MEMTEST_SCRATCH
38320cf350SYoshihiro Shimoda #undef	CONFIG_SYS_LOADS_BAUD_CHANGE
39320cf350SYoshihiro Shimoda 
40320cf350SYoshihiro Shimoda #define CONFIG_SYS_SDRAM_BASE		(SH7753EVB_SDRAM_BASE)
41320cf350SYoshihiro Shimoda #define CONFIG_SYS_SDRAM_SIZE		(SH7753EVB_SDRAM_SIZE)
42320cf350SYoshihiro Shimoda #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
43320cf350SYoshihiro Shimoda 					 128 * 1024 * 1024)
44320cf350SYoshihiro Shimoda 
45320cf350SYoshihiro Shimoda #define CONFIG_SYS_MONITOR_BASE		0x00000000
46320cf350SYoshihiro Shimoda #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
47320cf350SYoshihiro Shimoda #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
48320cf350SYoshihiro Shimoda #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
49320cf350SYoshihiro Shimoda 
50320cf350SYoshihiro Shimoda /* Ether */
51320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER			1
52320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_PORT	0
53320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_ADDR	18
54320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
55320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_GETHER	1
56320cf350SYoshihiro Shimoda #define CONFIG_BITBANGMII
57320cf350SYoshihiro Shimoda #define CONFIG_BITBANGMII_MULTI
58320cf350SYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
59320cf350SYoshihiro Shimoda #define CONFIG_PHY_VITESSE
60320cf350SYoshihiro Shimoda 
61320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_MAC_BASE_SPI	0x00090000
62320cf350SYoshihiro Shimoda #define SH7753EVB_SPI_SECTOR_SIZE	(64 * 1024)
63320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_MAC_BASE	SH7753EVB_ETHERNET_MAC_BASE_SPI
64320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_MAC_SIZE	17
65320cf350SYoshihiro Shimoda #define SH7753EVB_ETHERNET_NUM_CH	2
66320cf350SYoshihiro Shimoda 
67320cf350SYoshihiro Shimoda /* SPI */
68320cf350SYoshihiro Shimoda #define CONFIG_SH_SPI_BASE		0xfe002000
69320cf350SYoshihiro Shimoda 
70320cf350SYoshihiro Shimoda /* MMCIF */
71320cf350SYoshihiro Shimoda #define CONFIG_SH_MMCIF			1
72320cf350SYoshihiro Shimoda #define CONFIG_SH_MMCIF_ADDR		0xffcb0000
73320cf350SYoshihiro Shimoda #define CONFIG_SH_MMCIF_CLK		48000000
74320cf350SYoshihiro Shimoda 
75320cf350SYoshihiro Shimoda /* ENV setting */
76320cf350SYoshihiro Shimoda #define CONFIG_ENV_IS_EMBEDDED
77320cf350SYoshihiro Shimoda #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
78320cf350SYoshihiro Shimoda #define CONFIG_ENV_ADDR		(0x00080000)
79320cf350SYoshihiro Shimoda #define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
80320cf350SYoshihiro Shimoda #define CONFIG_ENV_OVERWRITE	1
81320cf350SYoshihiro Shimoda #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
82320cf350SYoshihiro Shimoda #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
83320cf350SYoshihiro Shimoda #define CONFIG_EXTRA_ENV_SETTINGS				\
84320cf350SYoshihiro Shimoda 		"netboot=bootp; bootm\0"
85320cf350SYoshihiro Shimoda 
86320cf350SYoshihiro Shimoda /* Board Clock */
87320cf350SYoshihiro Shimoda #define CONFIG_SYS_CLK_FREQ	48000000
88320cf350SYoshihiro Shimoda #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
89320cf350SYoshihiro Shimoda #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
90320cf350SYoshihiro Shimoda #define CONFIG_SYS_TMU_CLK_DIV	4
91320cf350SYoshihiro Shimoda #endif	/* __SH7753EVB_H */
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