xref: /rk3399_rockchip-uboot/include/configs/sh7752evb.h (revision 1a2621bab89c3fd6bd09a601b0b94dc26e238d7c)
1*1a2621baSYoshihiro Shimoda /*
2*1a2621baSYoshihiro Shimoda  * Configuation settings for the sh7752evb board
3*1a2621baSYoshihiro Shimoda  *
4*1a2621baSYoshihiro Shimoda  * Copyright (C) 2012 Renesas Solutions Corp.
5*1a2621baSYoshihiro Shimoda  *
6*1a2621baSYoshihiro Shimoda  * See file CREDITS for list of people who contributed to this
7*1a2621baSYoshihiro Shimoda  * project.
8*1a2621baSYoshihiro Shimoda  *
9*1a2621baSYoshihiro Shimoda  * This program is free software; you can redistribute it and/or
10*1a2621baSYoshihiro Shimoda  * modify it under the terms of the GNU General Public License as
11*1a2621baSYoshihiro Shimoda  * published by the Free Software Foundation; either version 2 of
12*1a2621baSYoshihiro Shimoda  * the License, or (at your option) any later version.
13*1a2621baSYoshihiro Shimoda  *
14*1a2621baSYoshihiro Shimoda  * This program is distributed in the hope that it will be useful,
15*1a2621baSYoshihiro Shimoda  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16*1a2621baSYoshihiro Shimoda  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17*1a2621baSYoshihiro Shimoda  * GNU General Public License for more details.
18*1a2621baSYoshihiro Shimoda  *
19*1a2621baSYoshihiro Shimoda  * You should have received a copy of the GNU General Public License
20*1a2621baSYoshihiro Shimoda  * along with this program; if not, write to the Free Software
21*1a2621baSYoshihiro Shimoda  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22*1a2621baSYoshihiro Shimoda  * MA 02111-1307 USA
23*1a2621baSYoshihiro Shimoda  */
24*1a2621baSYoshihiro Shimoda 
25*1a2621baSYoshihiro Shimoda #ifndef __SH7752EVB_H
26*1a2621baSYoshihiro Shimoda #define __SH7752EVB_H
27*1a2621baSYoshihiro Shimoda 
28*1a2621baSYoshihiro Shimoda #undef DEBUG
29*1a2621baSYoshihiro Shimoda #define CONFIG_SH		1
30*1a2621baSYoshihiro Shimoda #define CONFIG_SH4A		1
31*1a2621baSYoshihiro Shimoda #define CONFIG_SH_32BIT		1
32*1a2621baSYoshihiro Shimoda #define CONFIG_CPU_SH7752	1
33*1a2621baSYoshihiro Shimoda #define CONFIG_SH7752EVB	1
34*1a2621baSYoshihiro Shimoda 
35*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_TEXT_BASE	0x5ff80000
36*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7752evb/u-boot.lds"
37*1a2621baSYoshihiro Shimoda 
38*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_MEMORY
39*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_NET
40*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_MII
41*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_PING
42*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_NFS
43*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_DFL
44*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_SDRAM
45*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_SF
46*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_RUN
47*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_SAVEENV
48*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_MD5SUM
49*1a2621baSYoshihiro Shimoda #define CONFIG_MD5
50*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_LOADS
51*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_MMC
52*1a2621baSYoshihiro Shimoda #define CONFIG_CMD_EXT2
53*1a2621baSYoshihiro Shimoda #define CONFIG_DOS_PARTITION
54*1a2621baSYoshihiro Shimoda #define CONFIG_MAC_PARTITION
55*1a2621baSYoshihiro Shimoda 
56*1a2621baSYoshihiro Shimoda #define CONFIG_BAUDRATE		115200
57*1a2621baSYoshihiro Shimoda #define CONFIG_BOOTDELAY	3
58*1a2621baSYoshihiro Shimoda #define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
59*1a2621baSYoshihiro Shimoda 
60*1a2621baSYoshihiro Shimoda #define CONFIG_VERSION_VARIABLE
61*1a2621baSYoshihiro Shimoda #undef	CONFIG_SHOW_BOOT_PROGRESS
62*1a2621baSYoshihiro Shimoda #define CONFIG_CMDLINE_EDITING
63*1a2621baSYoshihiro Shimoda #define CONFIG_AUTO_COMPLETE
64*1a2621baSYoshihiro Shimoda 
65*1a2621baSYoshihiro Shimoda /* MEMORY */
66*1a2621baSYoshihiro Shimoda #define SH7752EVB_SDRAM_BASE		(0x40000000)
67*1a2621baSYoshihiro Shimoda #define SH7752EVB_SDRAM_SIZE		(512 * 1024 * 1024)
68*1a2621baSYoshihiro Shimoda 
69*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_LONGHELP
70*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_PROMPT		"=> "
71*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_CBSIZE		256
72*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_PBSIZE		256
73*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_MAXARGS		16
74*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_BARGSIZE		512
75*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
76*1a2621baSYoshihiro Shimoda 
77*1a2621baSYoshihiro Shimoda /* SCIF */
78*1a2621baSYoshihiro Shimoda #define CONFIG_SCIF_CONSOLE	1
79*1a2621baSYoshihiro Shimoda #define CONFIG_CONS_SCIF2	1
80*1a2621baSYoshihiro Shimoda #undef	CONFIG_SYS_CONSOLE_INFO_QUIET
81*1a2621baSYoshihiro Shimoda #undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
82*1a2621baSYoshihiro Shimoda #undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
83*1a2621baSYoshihiro Shimoda 
84*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_START	(SH7752EVB_SDRAM_BASE)
85*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
86*1a2621baSYoshihiro Shimoda 					 480 * 1024 * 1024)
87*1a2621baSYoshihiro Shimoda #undef	CONFIG_SYS_ALT_MEMTEST
88*1a2621baSYoshihiro Shimoda #undef	CONFIG_SYS_MEMTEST_SCRATCH
89*1a2621baSYoshihiro Shimoda #undef	CONFIG_SYS_LOADS_BAUD_CHANGE
90*1a2621baSYoshihiro Shimoda 
91*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_SDRAM_BASE		(SH7752EVB_SDRAM_BASE)
92*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_SDRAM_SIZE		(SH7752EVB_SDRAM_SIZE)
93*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
94*1a2621baSYoshihiro Shimoda 					 128 * 1024 * 1024)
95*1a2621baSYoshihiro Shimoda 
96*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_MONITOR_BASE		0x00000000
97*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
98*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
99*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
100*1a2621baSYoshihiro Shimoda 
101*1a2621baSYoshihiro Shimoda /* FLASH */
102*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_NO_FLASH
103*1a2621baSYoshihiro Shimoda 
104*1a2621baSYoshihiro Shimoda /* Ether */
105*1a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER			1
106*1a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_PORT	0
107*1a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_ADDR	18
108*1a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
109*1a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_GETHER	1
110*1a2621baSYoshihiro Shimoda #define CONFIG_PHYLIB
111*1a2621baSYoshihiro Shimoda #define CONFIG_BITBANGMII
112*1a2621baSYoshihiro Shimoda #define CONFIG_BITBANGMII_MULTI
113*1a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
114*1a2621baSYoshihiro Shimoda #define CONFIG_PHY_VITESSE
115*1a2621baSYoshihiro Shimoda 
116*1a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_BASE_SPI	0x00090000
117*1a2621baSYoshihiro Shimoda #define SH7752EVB_SPI_SECTOR_SIZE	(64 * 1024)
118*1a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_BASE	SH7752EVB_ETHERNET_MAC_BASE_SPI
119*1a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_SIZE	17
120*1a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_NUM_CH	2
121*1a2621baSYoshihiro Shimoda #define CONFIG_BOARD_LATE_INIT
122*1a2621baSYoshihiro Shimoda 
123*1a2621baSYoshihiro Shimoda /* SPI */
124*1a2621baSYoshihiro Shimoda #define CONFIG_SH_SPI			1
125*1a2621baSYoshihiro Shimoda #define CONFIG_SH_SPI_BASE		0xfe002000
126*1a2621baSYoshihiro Shimoda #define CONFIG_SPI_FLASH
127*1a2621baSYoshihiro Shimoda #define CONFIG_SPI_FLASH_STMICRO	1
128*1a2621baSYoshihiro Shimoda #define CONFIG_SPI_FLASH_MACRONIX	1
129*1a2621baSYoshihiro Shimoda 
130*1a2621baSYoshihiro Shimoda /* MMCIF */
131*1a2621baSYoshihiro Shimoda #define CONFIG_MMC			1
132*1a2621baSYoshihiro Shimoda #define CONFIG_GENERIC_MMC		1
133*1a2621baSYoshihiro Shimoda #define CONFIG_SH_MMCIF			1
134*1a2621baSYoshihiro Shimoda #define CONFIG_SH_MMCIF_ADDR		0xffcb0000
135*1a2621baSYoshihiro Shimoda #define CONFIG_SH_MMCIF_CLK		48000000
136*1a2621baSYoshihiro Shimoda 
137*1a2621baSYoshihiro Shimoda /* ENV setting */
138*1a2621baSYoshihiro Shimoda #define CONFIG_ENV_IS_EMBEDDED
139*1a2621baSYoshihiro Shimoda #define CONFIG_ENV_IS_IN_SPI_FLASH
140*1a2621baSYoshihiro Shimoda #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
141*1a2621baSYoshihiro Shimoda #define CONFIG_ENV_ADDR		(0x00080000)
142*1a2621baSYoshihiro Shimoda #define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
143*1a2621baSYoshihiro Shimoda #define CONFIG_ENV_OVERWRITE	1
144*1a2621baSYoshihiro Shimoda #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
145*1a2621baSYoshihiro Shimoda #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
146*1a2621baSYoshihiro Shimoda #define CONFIG_EXTRA_ENV_SETTINGS				\
147*1a2621baSYoshihiro Shimoda 		"netboot=bootp; bootm\0"
148*1a2621baSYoshihiro Shimoda 
149*1a2621baSYoshihiro Shimoda /* Board Clock */
150*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_CLK_FREQ	48000000
151*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_TMU_CLK_DIV	4
152*1a2621baSYoshihiro Shimoda #define CONFIG_SYS_HZ		1000
153*1a2621baSYoshihiro Shimoda #endif	/* __SH7752EVB_H */
154