xref: /rk3399_rockchip-uboot/include/configs/sh7752evb.h (revision 99c184906c6e99d402edd816dcb78fcb9ef0f923)
11a2621baSYoshihiro Shimoda /*
21a2621baSYoshihiro Shimoda  * Configuation settings for the sh7752evb board
31a2621baSYoshihiro Shimoda  *
41a2621baSYoshihiro Shimoda  * Copyright (C) 2012 Renesas Solutions Corp.
51a2621baSYoshihiro Shimoda  *
61a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
71a2621baSYoshihiro Shimoda  */
81a2621baSYoshihiro Shimoda 
91a2621baSYoshihiro Shimoda #ifndef __SH7752EVB_H
101a2621baSYoshihiro Shimoda #define __SH7752EVB_H
111a2621baSYoshihiro Shimoda 
121a2621baSYoshihiro Shimoda #define CONFIG_CPU_SH7752	1
131a2621baSYoshihiro Shimoda #define CONFIG_SH7752EVB	1
141a2621baSYoshihiro Shimoda 
151a2621baSYoshihiro Shimoda #define CONFIG_SYS_TEXT_BASE	0x5ff80000
161a2621baSYoshihiro Shimoda 
17*18a40e84SVladimir Zapolskiy #define CONFIG_DISPLAY_BOARDINFO
181a2621baSYoshihiro Shimoda #undef	CONFIG_SHOW_BOOT_PROGRESS
191a2621baSYoshihiro Shimoda #define CONFIG_CMDLINE_EDITING
201a2621baSYoshihiro Shimoda #define CONFIG_AUTO_COMPLETE
211a2621baSYoshihiro Shimoda 
221a2621baSYoshihiro Shimoda /* MEMORY */
231a2621baSYoshihiro Shimoda #define SH7752EVB_SDRAM_BASE		(0x40000000)
241a2621baSYoshihiro Shimoda #define SH7752EVB_SDRAM_SIZE		(512 * 1024 * 1024)
251a2621baSYoshihiro Shimoda 
261a2621baSYoshihiro Shimoda #define CONFIG_SYS_LONGHELP
271a2621baSYoshihiro Shimoda #define CONFIG_SYS_PBSIZE		256
281a2621baSYoshihiro Shimoda #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
291a2621baSYoshihiro Shimoda 
301a2621baSYoshihiro Shimoda /* SCIF */
311a2621baSYoshihiro Shimoda #define CONFIG_CONS_SCIF2	1
321a2621baSYoshihiro Shimoda 
331a2621baSYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_START	(SH7752EVB_SDRAM_BASE)
341a2621baSYoshihiro Shimoda #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
351a2621baSYoshihiro Shimoda 					 480 * 1024 * 1024)
361a2621baSYoshihiro Shimoda #undef	CONFIG_SYS_ALT_MEMTEST
371a2621baSYoshihiro Shimoda #undef	CONFIG_SYS_MEMTEST_SCRATCH
381a2621baSYoshihiro Shimoda #undef	CONFIG_SYS_LOADS_BAUD_CHANGE
391a2621baSYoshihiro Shimoda 
401a2621baSYoshihiro Shimoda #define CONFIG_SYS_SDRAM_BASE		(SH7752EVB_SDRAM_BASE)
411a2621baSYoshihiro Shimoda #define CONFIG_SYS_SDRAM_SIZE		(SH7752EVB_SDRAM_SIZE)
421a2621baSYoshihiro Shimoda #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
431a2621baSYoshihiro Shimoda 					 128 * 1024 * 1024)
441a2621baSYoshihiro Shimoda 
451a2621baSYoshihiro Shimoda #define CONFIG_SYS_MONITOR_BASE		0x00000000
461a2621baSYoshihiro Shimoda #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
471a2621baSYoshihiro Shimoda #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
481a2621baSYoshihiro Shimoda #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
491a2621baSYoshihiro Shimoda 
501a2621baSYoshihiro Shimoda /* Ether */
511a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER			1
521a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_PORT	0
531a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_ADDR	18
541a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
551a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_USE_GETHER	1
561a2621baSYoshihiro Shimoda #define CONFIG_BITBANGMII
571a2621baSYoshihiro Shimoda #define CONFIG_BITBANGMII_MULTI
581a2621baSYoshihiro Shimoda #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
591a2621baSYoshihiro Shimoda #define CONFIG_PHY_VITESSE
601a2621baSYoshihiro Shimoda 
611a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_BASE_SPI	0x00090000
621a2621baSYoshihiro Shimoda #define SH7752EVB_SPI_SECTOR_SIZE	(64 * 1024)
631a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_BASE	SH7752EVB_ETHERNET_MAC_BASE_SPI
641a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_MAC_SIZE	17
651a2621baSYoshihiro Shimoda #define SH7752EVB_ETHERNET_NUM_CH	2
661a2621baSYoshihiro Shimoda 
671a2621baSYoshihiro Shimoda /* SPI */
681a2621baSYoshihiro Shimoda #define CONFIG_SH_SPI_BASE		0xfe002000
691a2621baSYoshihiro Shimoda 
701a2621baSYoshihiro Shimoda /* MMCIF */
711a2621baSYoshihiro Shimoda #define CONFIG_SH_MMCIF			1
721a2621baSYoshihiro Shimoda #define CONFIG_SH_MMCIF_ADDR		0xffcb0000
731a2621baSYoshihiro Shimoda #define CONFIG_SH_MMCIF_CLK		48000000
741a2621baSYoshihiro Shimoda 
751a2621baSYoshihiro Shimoda /* ENV setting */
761a2621baSYoshihiro Shimoda #define CONFIG_ENV_IS_EMBEDDED
771a2621baSYoshihiro Shimoda #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
781a2621baSYoshihiro Shimoda #define CONFIG_ENV_ADDR		(0x00080000)
791a2621baSYoshihiro Shimoda #define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
801a2621baSYoshihiro Shimoda #define CONFIG_ENV_OVERWRITE	1
811a2621baSYoshihiro Shimoda #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
821a2621baSYoshihiro Shimoda #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
831a2621baSYoshihiro Shimoda #define CONFIG_EXTRA_ENV_SETTINGS				\
841a2621baSYoshihiro Shimoda 		"netboot=bootp; bootm\0"
851a2621baSYoshihiro Shimoda 
861a2621baSYoshihiro Shimoda /* Board Clock */
871a2621baSYoshihiro Shimoda #define CONFIG_SYS_CLK_FREQ	48000000
88684a501eSNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
89684a501eSNobuhiro Iwamatsu #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
901a2621baSYoshihiro Shimoda #define CONFIG_SYS_TMU_CLK_DIV	4
911a2621baSYoshihiro Shimoda #endif	/* __SH7752EVB_H */
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